diff mbox

[3/3] arm: dts: mt2701: Add display subsystem related nodes for MT2701

Message ID 1496297324-21091-4-git-send-email-erin.lo@mediatek.com (mailing list archive)
State New, archived
Headers show

Commit Message

Erin Lo June 1, 2017, 6:08 a.m. UTC 
From: YT Shen <yt.shen@mediatek.com>

This patch adds the device nodes for the DISP function blocks for MT2701

Signed-off-by: YT Shen <yt.shen@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 84 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

Comments

Matthias Brugger June 9, 2017, 8:14 a.m. UTC | #1 
On 01/06/17 08:08, Erin Lo wrote:
> From: YT Shen <yt.shen@mediatek.com>
> 
> This patch adds the device nodes for the DISP function blocks for MT2701
> 
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>   arch/arm/boot/dts/mt2701.dtsi | 84 +++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 84 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 4f110d5..e20b65c 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -17,6 +17,7 @@
>   #include <dt-bindings/interrupt-controller/irq.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/reset/mt2701-resets.h>
> +#include <dt-bindings/memory/mt2701-larb-port.h>
>   #include "skeleton64.dtsi"
>   #include "mt2701-pinfunc.h"
>   
> @@ -24,6 +25,11 @@
>   	compatible = "mediatek,mt2701";
>   	interrupt-parent = <&sysirq>;
>   
> +	aliases {
> +		rdma0 = &rdma0;
> +		rdma1 = &rdma1;
> +	};
> +

I know we have this alias in mt8173.dtsi, but I don't understand what 
they are for. Do you know?

Regards,
Matthias
Philipp Zabel June 9, 2017, 8:22 a.m. UTC | #2 
Hi Matthias,

On Fri, 2017-06-09 at 10:14 +0200, Matthias Brugger wrote:
> 
> On 01/06/17 08:08, Erin Lo wrote:
> > From: YT Shen <yt.shen@mediatek.com>
> > 
> > This patch adds the device nodes for the DISP function blocks for MT2701
> > 
> > Signed-off-by: YT Shen <yt.shen@mediatek.com>
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
> >   arch/arm/boot/dts/mt2701.dtsi | 84 +++++++++++++++++++++++++++++++++++++++++++
> >   1 file changed, 84 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index 4f110d5..e20b65c 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -17,6 +17,7 @@
> >   #include <dt-bindings/interrupt-controller/irq.h>
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >   #include <dt-bindings/reset/mt2701-resets.h>
> > +#include <dt-bindings/memory/mt2701-larb-port.h>
> >   #include "skeleton64.dtsi"
> >   #include "mt2701-pinfunc.h"
> >   
> > @@ -24,6 +25,11 @@
> >   	compatible = "mediatek,mt2701";
> >   	interrupt-parent = <&sysirq>;
> >   
> > +	aliases {
> > +		rdma0 = &rdma0;
> > +		rdma1 = &rdma1;
> > +	};
> > +
> 
> I know we have this alias in mt8173.dtsi, but I don't understand what 
> they are for. Do you know?

The mtk_disp_rdma platform driver uses mtk_ddp_comp_get_id() to identify
the specific RDMA instance, which calls of_alias_get_id(). The core code
needs to know which RDMA is which to correctly set up the display data
paths.

regards
Philipp
Matthias Brugger June 9, 2017, 10:59 a.m. UTC | #3 
On 09/06/17 10:22, Philipp Zabel wrote:
> Hi Matthias,
> 
> On Fri, 2017-06-09 at 10:14 +0200, Matthias Brugger wrote:
>>
>> On 01/06/17 08:08, Erin Lo wrote:
>>> From: YT Shen <yt.shen@mediatek.com>
>>>
>>> This patch adds the device nodes for the DISP function blocks for MT2701
>>>
>>> Signed-off-by: YT Shen <yt.shen@mediatek.com>
>>> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
>>> ---
>>>    arch/arm/boot/dts/mt2701.dtsi | 84 +++++++++++++++++++++++++++++++++++++++++++
>>>    1 file changed, 84 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
>>> index 4f110d5..e20b65c 100644
>>> --- a/arch/arm/boot/dts/mt2701.dtsi
>>> +++ b/arch/arm/boot/dts/mt2701.dtsi
>>> @@ -17,6 +17,7 @@
>>>    #include <dt-bindings/interrupt-controller/irq.h>
>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>    #include <dt-bindings/reset/mt2701-resets.h>
>>> +#include <dt-bindings/memory/mt2701-larb-port.h>
>>>    #include "skeleton64.dtsi"
>>>    #include "mt2701-pinfunc.h"
>>>    
>>> @@ -24,6 +25,11 @@
>>>    	compatible = "mediatek,mt2701";
>>>    	interrupt-parent = <&sysirq>;
>>>    
>>> +	aliases {
>>> +		rdma0 = &rdma0;
>>> +		rdma1 = &rdma1;
>>> +	};
>>> +
>>
>> I know we have this alias in mt8173.dtsi, but I don't understand what
>> they are for. Do you know?
> 
> The mtk_disp_rdma platform driver uses mtk_ddp_comp_get_id() to identify
> the specific RDMA instance, which calls of_alias_get_id(). The core code
> needs to know which RDMA is which to correctly set up the display data
> paths.
> 

Ok, thanks for the clarification!

Matthias
Matthias Brugger June 12, 2017, 9:13 a.m. UTC | #4 
On 01/06/17 08:08, Erin Lo wrote:
> From: YT Shen <yt.shen@mediatek.com>
> 
> This patch adds the device nodes for the DISP function blocks for MT2701
> 
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>   arch/arm/boot/dts/mt2701.dtsi | 84 +++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 84 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 4f110d5..e20b65c 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -17,6 +17,7 @@
>   #include <dt-bindings/interrupt-controller/irq.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/reset/mt2701-resets.h>
> +#include <dt-bindings/memory/mt2701-larb-port.h>
>   #include "skeleton64.dtsi"
>   #include "mt2701-pinfunc.h"
>   
> @@ -24,6 +25,11 @@
>   	compatible = "mediatek,mt2701";
>   	interrupt-parent = <&sysirq>;
>   
> +	aliases {
> +		rdma0 = &rdma0;
> +		rdma1 = &rdma1;
> +	};
> +
>   	cpus {
>   		#address-cells = <1>;
>   		#size-cells = <0>;
> @@ -201,6 +207,16 @@
>   		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>   	};
>   
> +	mipi_tx0: mipi-dphy@10010000 {
> +		compatible = "mediatek,mt2701-mipi-tx";
> +		reg = <0 0x10010000 0 0x90>;
> +		clocks = <&clk26m>;
> +		clock-output-names = "mipi_tx0_pll";
> +		#clock-cells = <0>;
> +		#phy-cells = <0>;
> +		status = "disabled";
> +	};
> +
>   	sysirq: interrupt-controller@10200100 {
>   		compatible = "mediatek,mt2701-sysirq",
>   			     "mediatek,mt6577-sysirq";
> @@ -366,6 +382,39 @@
>   		#clock-cells = <1>;
>   	};
>   
> +	display_components: dispsys@14000000 {
> +		compatible = "mediatek,mt2701-mmsys";
> +		reg = <0 0x14000000 0 0x1000>;
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> +	};

Can you please rebase on a recent kernel version. mt2701-mmsys node is 
already present.

Thanks,
Matthias

> +
> +	ovl@14007000 {
> +		compatible = "mediatek,mt2701-disp-ovl";
> +		reg = <0 0x14007000 0 0x1000>;
> +		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&mmsys CLK_MM_DISP_OVL>;
> +		iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
> +		mediatek,larb = <&larb0>;
> +	};
> +
> +	rdma0: rdma@14008000 {
> +		compatible = "mediatek,mt2701-disp-rdma";
> +		reg = <0 0x14008000 0 0x1000>;
> +		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&mmsys CLK_MM_DISP_RDMA>;
> +		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
> +		mediatek,larb = <&larb0>;
> +	};
> +
> +	wdma@14009000 {
> +		compatible = "mediatek,mt2701-disp-wdma";
> +		reg = <0 0x14009000 0 0x1000>;
> +		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&mmsys CLK_MM_DISP_WDMA>;
> +		iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
> +		mediatek,larb = <&larb0>;
> +	};
> +
>   	bls: bls@1400a000 {
>   		compatible = "mediatek,mt2701-disp-pwm";
>   		reg = <0 0x1400a000 0 0x1000>;
> @@ -375,6 +424,32 @@
>   		status = "disabled";
>   	};
>   
> +	color@1400b000 {
> +		compatible = "mediatek,mt2701-disp-color";
> +		reg = <0 0x1400b000 0 0x1000>;
> +		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&mmsys CLK_MM_DISP_COLOR>;
> +	};
> +
> +	dsi: dsi@1400c000 {
> +		compatible = "mediatek,mt2701-dsi";
> +		reg = <0 0x1400c000 0 0x1000>;
> +		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIG>,
> +			 <&mipi_tx0>;
> +		clock-names = "engine", "digital", "hs";
> +		phys = <&mipi_tx0>;
> +		phy-names = "dphy";
> +		status = "disabled";
> +	};
> +
> +	mutex: mutex@1400e000 {
> +		compatible = "mediatek,mt2701-disp-mutex";
> +		reg = <0 0x1400e000 0 0x1000>;
> +		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&mmsys CLK_MM_MUTEX_32K>;
> +	};
> +
>   	larb0: larb@14010000 {
>   		compatible = "mediatek,mt2701-smi-larb";
>   		reg = <0 0x14010000 0 0x1000>;
> @@ -385,6 +460,15 @@
>   		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
>   	};
>   
> +	rdma1: rdma@14012000 {
> +		compatible = "mediatek,mt2701-disp-rdma";
> +		reg = <0 0x14012000 0 0x1000>;
> +		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> +		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
> +		mediatek,larb = <&larb0>;
> +	};
> +
>   	imgsys: syscon@15000000 {
>   		compatible = "mediatek,mt2701-imgsys", "syscon";
>   		reg = <0 0x15000000 0 0x1000>;
>
YT Shen June 16, 2017, 1:54 p.m. UTC | #5 
On Mon, 2017-06-12 at 11:13 +0200, Matthias Brugger wrote:
> 
> On 01/06/17 08:08, Erin Lo wrote:
> > From: YT Shen <yt.shen@mediatek.com>
> > 
> > This patch adds the device nodes for the DISP function blocks for MT2701
> > 
> > Signed-off-by: YT Shen <yt.shen@mediatek.com>
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
> >   arch/arm/boot/dts/mt2701.dtsi | 84 +++++++++++++++++++++++++++++++++++++++++++
> >   1 file changed, 84 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index 4f110d5..e20b65c 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -17,6 +17,7 @@
> >   #include <dt-bindings/interrupt-controller/irq.h>
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >   #include <dt-bindings/reset/mt2701-resets.h>
> > +#include <dt-bindings/memory/mt2701-larb-port.h>
> >   #include "skeleton64.dtsi"
> >   #include "mt2701-pinfunc.h"
> >   
> > @@ -24,6 +25,11 @@
> >   	compatible = "mediatek,mt2701";
> >   	interrupt-parent = <&sysirq>;
> >   
> > +	aliases {
> > +		rdma0 = &rdma0;
> > +		rdma1 = &rdma1;
> > +	};
> > +
> >   	cpus {
> >   		#address-cells = <1>;
> >   		#size-cells = <0>;
> > @@ -201,6 +207,16 @@
> >   		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> >   	};
> >   
> > +	mipi_tx0: mipi-dphy@10010000 {
> > +		compatible = "mediatek,mt2701-mipi-tx";
> > +		reg = <0 0x10010000 0 0x90>;
> > +		clocks = <&clk26m>;
> > +		clock-output-names = "mipi_tx0_pll";
> > +		#clock-cells = <0>;
> > +		#phy-cells = <0>;
> > +		status = "disabled";
> > +	};
> > +
> >   	sysirq: interrupt-controller@10200100 {
> >   		compatible = "mediatek,mt2701-sysirq",
> >   			     "mediatek,mt6577-sysirq";
> > @@ -366,6 +382,39 @@
> >   		#clock-cells = <1>;
> >   	};
> >   
> > +	display_components: dispsys@14000000 {
> > +		compatible = "mediatek,mt2701-mmsys";
> > +		reg = <0 0x14000000 0 0x1000>;
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> > +	};
> 
> Can you please rebase on a recent kernel version. mt2701-mmsys node is 
> already present.
> 
> Thanks,
> Matthias
OK, we will rebase the mt2701 device tree in the next version.
Thanks.

yt.shen

> 
> > +
> > +	ovl@14007000 {
> > +		compatible = "mediatek,mt2701-disp-ovl";
> > +		reg = <0 0x14007000 0 0x1000>;
> > +		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_DISP_OVL>;
> > +		iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
> > +		mediatek,larb = <&larb0>;
> > +	};
> > +
> > +	rdma0: rdma@14008000 {
> > +		compatible = "mediatek,mt2701-disp-rdma";
> > +		reg = <0 0x14008000 0 0x1000>;
> > +		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_DISP_RDMA>;
> > +		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
> > +		mediatek,larb = <&larb0>;
> > +	};
> > +
> > +	wdma@14009000 {
> > +		compatible = "mediatek,mt2701-disp-wdma";
> > +		reg = <0 0x14009000 0 0x1000>;
> > +		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_DISP_WDMA>;
> > +		iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
> > +		mediatek,larb = <&larb0>;
> > +	};
> > +
> >   	bls: bls@1400a000 {
> >   		compatible = "mediatek,mt2701-disp-pwm";
> >   		reg = <0 0x1400a000 0 0x1000>;
> > @@ -375,6 +424,32 @@
> >   		status = "disabled";
> >   	};
> >   
> > +	color@1400b000 {
> > +		compatible = "mediatek,mt2701-disp-color";
> > +		reg = <0 0x1400b000 0 0x1000>;
> > +		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_DISP_COLOR>;
> > +	};
> > +
> > +	dsi: dsi@1400c000 {
> > +		compatible = "mediatek,mt2701-dsi";
> > +		reg = <0 0x1400c000 0 0x1000>;
> > +		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIG>,
> > +			 <&mipi_tx0>;
> > +		clock-names = "engine", "digital", "hs";
> > +		phys = <&mipi_tx0>;
> > +		phy-names = "dphy";
> > +		status = "disabled";
> > +	};
> > +
> > +	mutex: mutex@1400e000 {
> > +		compatible = "mediatek,mt2701-disp-mutex";
> > +		reg = <0 0x1400e000 0 0x1000>;
> > +		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_MUTEX_32K>;
> > +	};
> > +
> >   	larb0: larb@14010000 {
> >   		compatible = "mediatek,mt2701-smi-larb";
> >   		reg = <0 0x14010000 0 0x1000>;
> > @@ -385,6 +460,15 @@
> >   		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> >   	};
> >   
> > +	rdma1: rdma@14012000 {
> > +		compatible = "mediatek,mt2701-disp-rdma";
> > +		reg = <0 0x14012000 0 0x1000>;
> > +		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> > +		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
> > +		mediatek,larb = <&larb0>;
> > +	};
> > +
> >   	imgsys: syscon@15000000 {
> >   		compatible = "mediatek,mt2701-imgsys", "syscon";
> >   		reg = <0 0x15000000 0 0x1000>;
> >
diff mbox

Patch

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 4f110d5..e20b65c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -17,6 +17,7 @@ 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/mt2701-resets.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
 #include "skeleton64.dtsi"
 #include "mt2701-pinfunc.h"
 
@@ -24,6 +25,11 @@ 
 	compatible = "mediatek,mt2701";
 	interrupt-parent = <&sysirq>;
 
+	aliases {
+		rdma0 = &rdma0;
+		rdma1 = &rdma1;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -201,6 +207,16 @@ 
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
 	};
 
+	mipi_tx0: mipi-dphy@10010000 {
+		compatible = "mediatek,mt2701-mipi-tx";
+		reg = <0 0x10010000 0 0x90>;
+		clocks = <&clk26m>;
+		clock-output-names = "mipi_tx0_pll";
+		#clock-cells = <0>;
+		#phy-cells = <0>;
+		status = "disabled";
+	};
+
 	sysirq: interrupt-controller@10200100 {
 		compatible = "mediatek,mt2701-sysirq",
 			     "mediatek,mt6577-sysirq";
@@ -366,6 +382,39 @@ 
 		#clock-cells = <1>;
 	};
 
+	display_components: dispsys@14000000 {
+		compatible = "mediatek,mt2701-mmsys";
+		reg = <0 0x14000000 0 0x1000>;
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+	};
+
+	ovl@14007000 {
+		compatible = "mediatek,mt2701-disp-ovl";
+		reg = <0 0x14007000 0 0x1000>;
+		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_DISP_OVL>;
+		iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
+		mediatek,larb = <&larb0>;
+	};
+
+	rdma0: rdma@14008000 {
+		compatible = "mediatek,mt2701-disp-rdma";
+		reg = <0 0x14008000 0 0x1000>;
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_DISP_RDMA>;
+		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
+		mediatek,larb = <&larb0>;
+	};
+
+	wdma@14009000 {
+		compatible = "mediatek,mt2701-disp-wdma";
+		reg = <0 0x14009000 0 0x1000>;
+		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_DISP_WDMA>;
+		iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
+		mediatek,larb = <&larb0>;
+	};
+
 	bls: bls@1400a000 {
 		compatible = "mediatek,mt2701-disp-pwm";
 		reg = <0 0x1400a000 0 0x1000>;
@@ -375,6 +424,32 @@ 
 		status = "disabled";
 	};
 
+	color@1400b000 {
+		compatible = "mediatek,mt2701-disp-color";
+		reg = <0 0x1400b000 0 0x1000>;
+		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_DISP_COLOR>;
+	};
+
+	dsi: dsi@1400c000 {
+		compatible = "mediatek,mt2701-dsi";
+		reg = <0 0x1400c000 0 0x1000>;
+		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIG>,
+			 <&mipi_tx0>;
+		clock-names = "engine", "digital", "hs";
+		phys = <&mipi_tx0>;
+		phy-names = "dphy";
+		status = "disabled";
+	};
+
+	mutex: mutex@1400e000 {
+		compatible = "mediatek,mt2701-disp-mutex";
+		reg = <0 0x1400e000 0 0x1000>;
+		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_MUTEX_32K>;
+	};
+
 	larb0: larb@14010000 {
 		compatible = "mediatek,mt2701-smi-larb";
 		reg = <0 0x14010000 0 0x1000>;
@@ -385,6 +460,15 @@ 
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
 	};
 
+	rdma1: rdma@14012000 {
+		compatible = "mediatek,mt2701-disp-rdma";
+		reg = <0 0x14012000 0 0x1000>;
+		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
+		mediatek,larb = <&larb0>;
+	};
+
 	imgsys: syscon@15000000 {
 		compatible = "mediatek,mt2701-imgsys", "syscon";
 		reg = <0 0x15000000 0 0x1000>;