From patchwork Thu Jun 28 10:45:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 10493557 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4912460230 for ; Thu, 28 Jun 2018 10:46:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 33DAA29991 for ; Thu, 28 Jun 2018 10:46:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2621B299D0; Thu, 28 Jun 2018 10:46:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, MAILING_LIST_MULTI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 68CDE29991 for ; Thu, 28 Jun 2018 10:46:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WiB+QUH/u/iAxxYKYgPueXAUPxKUVUFhTPgTIzeKN+s=; b=FvKsl7ilzhqHlc X91VGIJN6ZFwg3AfGexTfCCv/gSH0JexONFi66aH4czOTufFsR7paPB7QWMSbelQJaXCSUoqV79bo HH/YXsbms2nj9XbU/YQR4hw7KzHSDT5KYCsraQgFrsKjLySQz1ta7zgs5pkYnxuU6MBf3G3ChQsD4 Hn9KvvJBpWOJHqCD3ML6HP3pCRiTyrUGwWtjVBLaNA7vBeBnwpQ2de7TBHzXNskwo3xxr7zVMp6nn pkPGIQIvuuAaRLypVqu/ySsAQAZ7rooFyAZYVKNxeFEss3VIz4kZ5MckIAEp0U5hIKdKejC7op7j1 N7C+eX1a0vqkDqgoMzaQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fYURO-0004zs-Fa for patchwork-linux-mediatek@patchwork.kernel.org; Thu, 28 Jun 2018 10:46:18 +0000 Received: from [210.61.82.184] (helo=mailgw02.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fYURB-0004qx-3d for linux-mediatek@lists.infradead.org; Thu, 28 Jun 2018 10:46:09 +0000 X-UUID: 06e328885deb4d0f9010e0348b33219c-20180628 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 918245787; Thu, 28 Jun 2018 18:45:49 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 28 Jun 2018 18:45:48 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 28 Jun 2018 18:45:48 +0800 From: Stanley Chu To: Matthias Brugger , Daniel Lezcano , Thomas Gleixner , Rob Herring Subject: [PATCH v3 4/5] clocksource/drivers/timer-mediatek: Convert the driver to timer-of Date: Thu, 28 Jun 2018 18:45:43 +0800 Message-ID: <1530182744-10731-5-git-send-email-stanley.chu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1530182744-10731-1-git-send-email-stanley.chu@mediatek.com> References: <1530182744-10731-1-git-send-email-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180628_034605_642643_F0B059AB X-CRM114-Status: GOOD ( 16.05 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Stanley Chu , linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, wsd_upstream@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Convert the driver to use the timer_of helpers. This allows to remove custom proprietary structure, factors out and simplifies the code. Signed-off-by: Stanley Chu --- drivers/clocksource/timer-mediatek.c | 222 ++++++++++++++++------------------ 1 file changed, 104 insertions(+), 118 deletions(-) diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c index ff284f2..d94d8e1 100644 --- a/drivers/clocksource/timer-mediatek.c +++ b/drivers/clocksource/timer-mediatek.c @@ -18,16 +18,13 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -#include #include +#include #include -#include #include -#include -#include -#include #include #include +#include "timer-of.h" #define GPT_IRQ_EN_REG 0x00 #define GPT_IRQ_ENABLE(val) BIT((val) - 1) @@ -56,49 +53,57 @@ #define GPT_CLK_EVT 1 #define GPT_CLK_SRC 2 -struct mtk_clock_event_device { - void __iomem *gpt_base; - u32 ticks_per_jiffy; - struct clock_event_device dev; +struct mtk_timer_private { + unsigned long ticks_per_jiffy; }; static void __iomem *gpt_sched_reg __read_mostly; -static u64 notrace mtk_gpt_read_sched_clock(void) +static void mtk_timer_of_priv_set(struct timer_of *to, u32 ticks_per_jiffy) { - return readl_relaxed(gpt_sched_reg); + struct mtk_timer_private *pd = to->private_data; + + pd->ticks_per_jiffy = ticks_per_jiffy; +} + +static void mtk_timer_of_priv_get(struct timer_of *to, + unsigned long *ticks_per_jiffy) +{ + struct mtk_timer_private *pd = to->private_data; + + if (ticks_per_jiffy) + *ticks_per_jiffy = pd->ticks_per_jiffy; } -static inline struct mtk_clock_event_device *to_mtk_clk( - struct clock_event_device *c) +static u64 notrace mtk_gpt_read_sched_clock(void) { - return container_of(c, struct mtk_clock_event_device, dev); + return readl_relaxed(gpt_sched_reg); } -static void mtk_gpt_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer) +static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer) { u32 val; - val = readl(evt->gpt_base + TIMER_CTRL_REG(timer)); - writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base + - TIMER_CTRL_REG(timer)); + val = readl(timer_of_base(to) + TIMER_CTRL_REG(timer)); + writel(val & ~TIMER_CTRL_ENABLE, timer_of_base(to) + + TIMER_CTRL_REG(timer)); } -static void mtk_gpt_clkevt_time_setup(struct mtk_clock_event_device *evt, - unsigned long delay, u8 timer) +static void mtk_gpt_clkevt_time_setup(struct timer_of *to, + unsigned long delay, u8 timer) { - writel(delay, evt->gpt_base + TIMER_CMP_REG(timer)); + writel(delay, timer_of_base(to) + TIMER_CMP_REG(timer)); } -static void mtk_gpt_clkevt_time_start(struct mtk_clock_event_device *evt, - bool periodic, u8 timer) +static void mtk_gpt_clkevt_time_start(struct timer_of *to, + bool periodic, u8 timer) { u32 val; /* Acknowledge interrupt */ - writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG); + writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG); - val = readl(evt->gpt_base + TIMER_CTRL_REG(timer)); + val = readl(timer_of_base(to) + TIMER_CTRL_REG(timer)); /* Clear 2 bit timer operation mode field */ val &= ~TIMER_CTRL_OP(0x3); @@ -109,160 +114,141 @@ static void mtk_gpt_clkevt_time_start(struct mtk_clock_event_device *evt, val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT); writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR, - evt->gpt_base + TIMER_CTRL_REG(timer)); + timer_of_base(to) + TIMER_CTRL_REG(timer)); } static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk) { - mtk_gpt_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT); + mtk_gpt_clkevt_time_stop(to_timer_of(clk), GPT_CLK_EVT); return 0; } static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk) { - struct mtk_clock_event_device *evt = to_mtk_clk(clk); + struct timer_of *to = to_timer_of(clk); + unsigned long ticks_per_jiffy; - mtk_gpt_clkevt_time_stop(evt, GPT_CLK_EVT); - mtk_gpt_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT); - mtk_gpt_clkevt_time_start(evt, true, GPT_CLK_EVT); + mtk_gpt_clkevt_time_stop(to, GPT_CLK_EVT); + mtk_timer_of_priv_get(to, &ticks_per_jiffy); + mtk_gpt_clkevt_time_setup(to, ticks_per_jiffy, GPT_CLK_EVT); + mtk_gpt_clkevt_time_start(to, true, GPT_CLK_EVT); return 0; } static int mtk_gpt_clkevt_next_event(unsigned long event, - struct clock_event_device *clk) + struct clock_event_device *clk) { - struct mtk_clock_event_device *evt = to_mtk_clk(clk); + struct timer_of *to = to_timer_of(clk); - mtk_gpt_clkevt_time_stop(evt, GPT_CLK_EVT); - mtk_gpt_clkevt_time_setup(evt, event, GPT_CLK_EVT); - mtk_gpt_clkevt_time_start(evt, false, GPT_CLK_EVT); + mtk_gpt_clkevt_time_stop(to, GPT_CLK_EVT); + mtk_gpt_clkevt_time_setup(to, event, GPT_CLK_EVT); + mtk_gpt_clkevt_time_start(to, false, GPT_CLK_EVT); return 0; } static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id) { - struct mtk_clock_event_device *evt = dev_id; + struct clock_event_device *clkevt = (struct clock_event_device *)dev_id; + struct timer_of *to = to_timer_of(clkevt); /* Acknowledge timer0 irq */ - writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG); - evt->dev.event_handler(&evt->dev); + writel(GPT_IRQ_ACK(GPT_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG); + clkevt->event_handler(clkevt); return IRQ_HANDLED; } static void -__init mtk_gpt_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option) +__init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option) { writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE, - evt->gpt_base + TIMER_CTRL_REG(timer)); + timer_of_base(to) + TIMER_CTRL_REG(timer)); writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1, - evt->gpt_base + TIMER_CLK_REG(timer)); + timer_of_base(to) + TIMER_CLK_REG(timer)); - writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer)); + writel(0x0, timer_of_base(to) + TIMER_CMP_REG(timer)); writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE, - evt->gpt_base + TIMER_CTRL_REG(timer)); + timer_of_base(to) + TIMER_CTRL_REG(timer)); } -static void mtk_gpt_enable_irq(struct mtk_clock_event_device *evt, u8 timer) +static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer) { u32 val; /* Disable all interrupts */ - writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG); + writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG); /* Acknowledge all spurious pending interrupts */ - writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG); + writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG); - val = readl(evt->gpt_base + GPT_IRQ_EN_REG); + val = readl(timer_of_base(to) + GPT_IRQ_EN_REG); writel(val | GPT_IRQ_ENABLE(timer), - evt->gpt_base + GPT_IRQ_EN_REG); + timer_of_base(to) + GPT_IRQ_EN_REG); } -static int __init mtk_gpt_init(struct device_node *node) -{ - struct mtk_clock_event_device *evt; - struct resource res; - unsigned long rate = 0; - struct clk *clk; - - evt = kzalloc(sizeof(*evt), GFP_KERNEL); - if (!evt) - return -ENOMEM; - - evt->dev.name = "mtk_tick"; - evt->dev.rating = 300; - evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - evt->dev.set_state_shutdown = mtk_gpt_clkevt_shutdown; - evt->dev.set_state_periodic = mtk_gpt_clkevt_set_periodic; - evt->dev.set_state_oneshot = mtk_gpt_clkevt_shutdown; - evt->dev.tick_resume = mtk_gpt_clkevt_shutdown; - evt->dev.set_next_event = mtk_gpt_clkevt_next_event; - evt->dev.cpumask = cpu_possible_mask; - - evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer-gpt"); - if (IS_ERR(evt->gpt_base)) { - pr_err("Can't get resource\n"); - goto err_kzalloc; - } +static struct timer_of to = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, - evt->dev.irq = irq_of_parse_and_map(node, 0); - if (evt->dev.irq <= 0) { - pr_err("Can't parse IRQ\n"); - goto err_mem; - } - - clk = of_clk_get(node, 0); - if (IS_ERR(clk)) { - pr_err("Can't get timer clock\n"); - goto err_irq; - } + .clkevt = { + .name = "mtk-clkevt", + .rating = 300, + .cpumask = cpu_possible_mask, + }, - if (clk_prepare_enable(clk)) { - pr_err("Can't prepare clock\n"); - goto err_clk_put; - } - rate = clk_get_rate(clk); + .of_irq = { + .flags = IRQF_TIMER | IRQF_IRQPOLL, + }, +}; - if (request_irq(evt->dev.irq, mtk_gpt_interrupt, - IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) { - pr_err("failed to setup irq %d\n", evt->dev.irq); - goto err_clk_disable; +static int __init mtk_gpt_init(struct device_node *node) +{ + int ret; + + to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown; + to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic; + to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown; + to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown; + to.clkevt.set_next_event = mtk_gpt_clkevt_next_event; + to.of_irq.handler = mtk_gpt_interrupt; + + ret = timer_of_init(node, &to); + if (ret) + goto err; + + to.private_data = kzalloc(sizeof(struct mtk_timer_private), + GFP_KERNEL); + + if (!to.private_data) { + ret = -ENOMEM; + goto deinit; } - evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); + mtk_timer_of_priv_set(&to, DIV_ROUND_UP(timer_of_rate(&to), HZ)); /* Configure clock source */ - mtk_gpt_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN); - clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC), - node->name, rate, 300, 32, clocksource_mmio_readl_up); - gpt_sched_reg = evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC); - sched_clock_register(mtk_gpt_read_sched_clock, 32, rate); + mtk_gpt_setup(&to, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN); + clocksource_mmio_init(timer_of_base(&to) + TIMER_CNT_REG(GPT_CLK_SRC), + node->name, timer_of_rate(&to), 300, 32, + clocksource_mmio_readl_up); + gpt_sched_reg = timer_of_base(&to) + TIMER_CNT_REG(GPT_CLK_SRC); + sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to)); /* Configure clock event */ - mtk_gpt_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT); - clockevents_config_and_register(&evt->dev, rate, 0x3, + mtk_gpt_setup(&to, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT); + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 0x3, 0xffffffff); - mtk_gpt_enable_irq(evt, GPT_CLK_EVT); + mtk_gpt_enable_irq(&to, GPT_CLK_EVT); return 0; -err_clk_disable: - clk_disable_unprepare(clk); -err_clk_put: - clk_put(clk); -err_irq: - irq_dispose_mapping(evt->dev.irq); -err_mem: - iounmap(evt->gpt_base); - of_address_to_resource(node, 0, &res); - release_mem_region(res.start, resource_size(&res)); -err_kzalloc: - kfree(evt); - - return -EINVAL; +deinit: + timer_of_cleanup(&to); +err: + return ret; } TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);