From patchwork Tue Jul 17 08:52:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mars Cheng X-Patchwork-Id: 10528497 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 07AB46020A for ; Tue, 17 Jul 2018 08:54:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DA52128C7B for ; Tue, 17 Jul 2018 08:54:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CDB7C28C94; Tue, 17 Jul 2018 08:54:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, MAILING_LIST_MULTI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6D26028C7B for ; Tue, 17 Jul 2018 08:54:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8NFhZih1OlmTV3tOUesT78Xkq6+2cDa1o9VMekyfQq4=; b=E9qLW1vnnk/qAw /B0WB8Jw4Zi4sY5nFV9MIsX0Vqi1zXufyzezGEo0HqAV8u4uenfwcJMaEeOGapNRaCFLxXyRvVSih srHUkiUdzbvv8ntV4bk7pwAbT7HHxcHZpcxmvGSQC7DZQ0DoejSlZFXKRkBHygg2X1LAZg8FgJ+Ar 7YDK3yowdZO4x+OaxLP4Yo1RDK8GY8+CMfgEHIXjQHBJIEBx+cJDvxNfysPxXjzIdHqjAGw8Uj3Dv NtAPF5rQkABsfdrB3TnlrXYgcyfzGQIGFo1XVTeUgHAkvnNHslwzCtm1dGjfAJGMnmI5gLXEzCQ+k 7+X9r1kx0PqZ6AfmY9Jw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1ffLkB-0001yP-Qk for patchwork-linux-mediatek@patchwork.kernel.org; Tue, 17 Jul 2018 08:54:03 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1ffLj9-0000TH-GD; Tue, 17 Jul 2018 08:53:03 +0000 X-UUID: f655682c0da7478d9716f1a84c0ce64a-20180717 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 701157985; Tue, 17 Jul 2018 16:52:37 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 17 Jul 2018 16:52:35 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 17 Jul 2018 16:52:35 +0800 From: Mars Cheng To: Matthias Brugger , Rob Herring , Marc Zyngier , Ryder Lee , Stephen Boyd , Sean Wang Subject: [PATCH v5 08/11] clk: mediatek: fix pll setting Date: Tue, 17 Jul 2018 16:52:29 +0800 Message-ID: <1531817552-17221-9-git-send-email-mars.cheng@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1531817552-17221-1-git-send-email-mars.cheng@mediatek.com> References: <1531817552-17221-1-git-send-email-mars.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180717_015259_884765_A74A150A X-CRM114-Status: GOOD ( 14.19 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, CC Hwang , wsd_upstream@mediatek.com, Loda Chou , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-serial@vger.kernel.org, Owen Chen , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Owen Chen 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits, add a variable to indicate this change and backward-compatible. 2. fmin: The pll freqency lower-bound is vary from 1GMhz to 1.5Ghz, add a variable to indicate platform-dependent. Signed-off-by: Owen Chen --- drivers/clk/mediatek/clk-mtk.h | 2 ++ drivers/clk/mediatek/clk-pll.c | 45 ++++++++++++++++++++++++++++++++++------ 2 files changed, 41 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f83c2bb..1882221 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -215,7 +215,9 @@ struct mtk_pll_data { const struct clk_ops *ops; u32 rst_bar_mask; unsigned long fmax; + unsigned long fmin; int pcwbits; + int pcwibits; uint32_t pcw_reg; int pcw_shift; const struct mtk_pll_div_table *div_table; diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index f54e401..df571e5 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -27,7 +27,7 @@ #define CON0_BASE_EN BIT(0) #define CON0_PWR_ON BIT(0) #define CON0_ISO_EN BIT(1) -#define CON0_PCW_CHG BIT(31) +#define CON1_PCW_CHG BIT(31) #define AUDPLL_TUNER_EN BIT(31) @@ -69,11 +69,13 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, { int pcwbits = pll->data->pcwbits; int pcwfbits; + int ibits; u64 vco; u8 c = 0; /* The fractional part of the PLL divider. */ - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; + pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0; vco = (u64)fin * pcw; @@ -93,9 +95,31 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, { u32 con1, val; int pll_en; + u32 tuner_en = 0; + u32 tuner_en_mask; + void __iomem *tuner_en_addr = NULL; pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; + /* disable tuner */ + if (pll->tuner_en_addr) { + tuner_en_addr = pll->tuner_en_addr; + tuner_en_mask = BIT(pll->data->tuner_en_bit); + } else if (pll->tuner_addr) { + tuner_en_addr = pll->tuner_addr; + tuner_en_mask = AUDPLL_TUNER_EN; + } + + if (tuner_en_addr) { + val = readl(tuner_en_addr); + tuner_en = val & tuner_en_mask; + + if (tuner_en) { + val &= ~tuner_en_mask; + writel(val, tuner_en_addr); + } + } + /* set postdiv */ val = readl(pll->pd_addr); val &= ~(POSTDIV_MASK << pll->data->pd_shift); @@ -116,12 +140,20 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, con1 = readl(pll->base_addr + REG_CON1); if (pll_en) - con1 |= CON0_PCW_CHG; + con1 |= CON1_PCW_CHG; writel(con1, pll->base_addr + REG_CON1); + if (pll->tuner_addr) writel(con1 + 1, pll->tuner_addr); + /* restore tuner_en */ + if (tuner_en_addr && tuner_en) { + val = readl(tuner_en_addr); + val |= tuner_en_mask; + writel(val, tuner_en_addr); + } + if (pll_en) udelay(20); } @@ -138,9 +170,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, u32 freq, u32 fin) { - unsigned long fmin = 1000 * MHZ; + unsigned long fmin = pll->data->fmin ? pll->data->fmin : 1000 * MHZ; const struct mtk_pll_div_table *div_table = pll->data->div_table; u64 _pcw; + int ibits; u32 val; if (freq > pll->data->fmax) @@ -164,7 +197,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, } /* _pcw = freq * postdiv / fin * 2^pcwfbits */ - _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS); + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; + _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits); do_div(_pcw, fin); *pcw = (u32)_pcw; @@ -192,7 +226,6 @@ static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK; postdiv = 1 << postdiv; - pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift; pcw &= GENMASK(pll->data->pcwbits - 1, 0);