diff mbox series

[v1,06/15] drm/mediatek: add memory mode for RDMA

Message ID 1532420235-22268-7-git-send-email-stu.hsieh@mediatek.com (mailing list archive)
State New, archived
Headers show
Series Add RDMA memory mode support for mediatek SOC MT2712 | expand

Commit Message

Stu Hsieh July 24, 2018, 8:17 a.m. UTC 
This patch add memory mode for RDMA

If use RDMA to read data from memory, it should set memory mode to RDMA

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

Comments

CK Hu (胡俊光) July 25, 2018, 2:40 a.m. UTC | #1 
Hi, Stu:

On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> This patch add memory mode for RDMA
> 
> If use RDMA to read data from memory, it should set memory mode to RDMA
> 
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 

[...]

>  static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
> @@ -111,7 +116,8 @@ static void mtk_rdma_start(struct mtk_ddp_comp *comp)
>  
>  static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
>  {
> -	rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
> +	writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
> +	writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);

Without reset, what happen to dram mode? Why direct link mode need not
this reset?

>  }
>  
>  static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> @@ -121,10 +127,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
>  	unsigned int threshold;
>  	unsigned int reg;
>  	struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> +	bool *rdma_memory_mode = comp->comp_mode;
>  
>  	rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
>  	rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
>  
> +	if (*rdma_memory_mode == true) {
> +		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
> +				 MATRIX_INT_MTX_SEL_DEFAULT);
> +		rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
> +				 RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
> +	}
> +

I would like this to be a kind of 'layer' config. In some SoC, one layer
of OVL could switch to direct link input or dram input. So I think it's
better to move this setting into some layer interface.

Regards,
CK

>  	/*
>  	 * Enable FIFO underflow since DSI and DPI can't be blocked.
>  	 * Keep the FIFO pseudo size reset default of 8 KiB. Set the
Stu Hsieh Aug. 2, 2018, 11:36 a.m. UTC | #2 
Hi, CK:

On Wed, 2018-07-25 at 10:40 +0800, CK Hu wrote:
> Hi, Stu:
> 
> On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> > This patch add memory mode for RDMA
> > 
> > If use RDMA to read data from memory, it should set memory mode to RDMA
> > 
> > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++++++++++++++-
> >  1 file changed, 15 insertions(+), 1 deletion(-)
> > 
> 
> [...]
> 
> >  static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
> > @@ -111,7 +116,8 @@ static void mtk_rdma_start(struct mtk_ddp_comp *comp)
> >  
> >  static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
> >  {
> > -	rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
> > +	writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
> > +	writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
> 
> Without reset, what happen to dram mode? Why direct link mode need not
> this reset?
> 

There is nothing to happen, I would remove it.

> >  }
> >  
> >  static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> > @@ -121,10 +127,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> >  	unsigned int threshold;
> >  	unsigned int reg;
> >  	struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> > +	bool *rdma_memory_mode = comp->comp_mode;
> >  
> >  	rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
> >  	rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
> >  
> > +	if (*rdma_memory_mode == true) {
> > +		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
> > +				 MATRIX_INT_MTX_SEL_DEFAULT);
> > +		rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
> > +				 RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
> > +	}
> > +
> 
> I would like this to be a kind of 'layer' config. In some SoC, one layer
> of OVL could switch to direct link input or dram input. So I think it's
> better to move this setting into some layer interface.
> 
> Regards,
> CK
> 

If move it to layer_config, RDMA would not trigger interrupt.
In the future, when cmdq patch upstream and accepted, this part can move
to layer_config. 

Regard,
Stu

> >  	/*
> >  	 * Enable FIFO underflow since DSI and DPI can't be blocked.
> >  	 * Keep the FIFO pseudo size reset default of 8 KiB. Set the
> 
>
CK Hu (胡俊光) Aug. 3, 2018, 7:30 a.m. UTC | #3 
Hi, Stu:

On Thu, 2018-08-02 at 19:36 +0800, Stu Hsieh wrote:
> Hi, CK:
> 
> On Wed, 2018-07-25 at 10:40 +0800, CK Hu wrote:
> > Hi, Stu:
> > 
> > On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> > > This patch add memory mode for RDMA
> > > 
> > > If use RDMA to read data from memory, it should set memory mode to RDMA
> > > 
> > > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> > > ---
> > >  drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++++++++++++++-
> > >  1 file changed, 15 insertions(+), 1 deletion(-)
> > > 
> > 
> > [...]
> > 
> > >  static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
> > > @@ -111,7 +116,8 @@ static void mtk_rdma_start(struct mtk_ddp_comp *comp)
> > >  
> > >  static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
> > >  {
> > > -	rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
> > > +	writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
> > > +	writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
> > 
> > Without reset, what happen to dram mode? Why direct link mode need not
> > this reset?
> > 
> 
> There is nothing to happen, I would remove it.
> 
> > >  }
> > >  
> > >  static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> > > @@ -121,10 +127,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> > >  	unsigned int threshold;
> > >  	unsigned int reg;
> > >  	struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> > > +	bool *rdma_memory_mode = comp->comp_mode;
> > >  
> > >  	rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
> > >  	rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
> > >  
> > > +	if (*rdma_memory_mode == true) {
> > > +		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
> > > +				 MATRIX_INT_MTX_SEL_DEFAULT);
> > > +		rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
> > > +				 RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
> > > +	}
> > > +
> > 
> > I would like this to be a kind of 'layer' config. In some SoC, one layer
> > of OVL could switch to direct link input or dram input. So I think it's
> > better to move this setting into some layer interface.
> > 
> > Regards,
> > CK
> > 
> 
> If move it to layer_config, RDMA would not trigger interrupt.
> In the future, when cmdq patch upstream and accepted, this part can move
> to layer_config. 

I don't know why interrupt would be influenced by moving this to layer
config? In mtk_crtc_ddp_hw_init(), call mtk_ddp_comp_config() first and
then call mtk_ddp_comp_layer_config() later. It's in almost the same
place.

Regards,
CK

> 
> Regard,
> Stu
> 
> > >  	/*
> > >  	 * Enable FIFO underflow since DSI and DPI can't be blocked.
> > >  	 * Keep the FIFO pseudo size reset default of 8 KiB. Set the
> > 
> > 
> 
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 60851bb2dd63..78a1a0057aff 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -31,6 +31,8 @@ 
 #define RDMA_REG_UPDATE_INT				BIT(0)
 #define DISP_REG_RDMA_GLOBAL_CON		0x0010
 #define RDMA_ENGINE_EN					BIT(0)
+#define RDMA_SOFT_RESET					BIT(4)
+#define RDMA_MODE_MEMORY				BIT(1)
 #define DISP_REG_RDMA_SIZE_CON_0		0x0014
 #define DISP_REG_RDMA_SIZE_CON_1		0x0018
 #define DISP_REG_RDMA_TARGET_LINE		0x001c
@@ -40,6 +42,8 @@ 
 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes)		((bytes) / 16)
 #define RDMA_FIFO_SIZE(rdma)			((rdma)->data->fifo_size)
 
+#define MATRIX_INT_MTX_SEL_DEFAULT		0xb00000
+
 struct mtk_disp_rdma_data {
 	unsigned int fifo_size;
 };
@@ -53,6 +57,7 @@  struct mtk_disp_rdma {
 	struct mtk_ddp_comp		ddp_comp;
 	struct drm_crtc			*crtc;
 	const struct mtk_disp_rdma_data	*data;
+	bool rdma_memory_mode;
 };
 
 static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
@@ -111,7 +116,8 @@  static void mtk_rdma_start(struct mtk_ddp_comp *comp)
 
 static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
 {
-	rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
+	writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
+	writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
 }
 
 static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
@@ -121,10 +127,18 @@  static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
 	unsigned int threshold;
 	unsigned int reg;
 	struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
+	bool *rdma_memory_mode = comp->comp_mode;
 
 	rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
 	rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
 
+	if (*rdma_memory_mode == true) {
+		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
+				 MATRIX_INT_MTX_SEL_DEFAULT);
+		rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
+				 RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
+	}
+
 	/*
 	 * Enable FIFO underflow since DSI and DPI can't be blocked.
 	 * Keep the FIFO pseudo size reset default of 8 KiB. Set the