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+* Mediatek seninf MIPI-CSI2 host driver
+
+Seninf MIPI-CSI2 host driver is a HW camera interface controller. It support a widely adopted,
+simple, high-speed protocol primarily intended for point-to-point image and video
+transmission between cameras and host devices.
+
+Required properties:
+ - compatible: "mediatek,mt8183-seninf"
+ - reg: Must contain an entry for each entry in reg-names.
+ - reg-names: Must include the following entries:
+ "base_reg": seninf registers base
+ "rx_reg": Rx analog registers base
+ - interrupts: interrupt number to the cpu.
+ - clocks : clock name from clock manager
+ - clock-names: must be CLK_CAM_SENINF and CLK_TOP_MUX_SENINF.
+ It is the clocks of seninf
+ - port : port for camera sensor
+ - port reg : must be '0' for camera 0, '1' for camera 1
+ - endpoint : config mipi-csi2 port setting for each camera
+ - data-lanes : the number of the data lane
+
+Example:
+ seninf: seninf@1a040000 {
+ compatible = "mediatek,mt8183_seninf";
+ reg = <0 0x1a040000 0 0x8000>,
+ <0 0x11C80000 0 0x6000>;
+ reg-names = "base_reg", "ana_reg";
+ interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>;
+ clocks =
+ <&camsys CLK_CAM_SENINF>, <&topckgen CLK_TOP_MUX_SENINF>;
+ clock-names =
+ "CLK_CAM_SENINF", "CLK_TOP_MUX_SENINF";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ mipi_in_cam0: endpoint@0 {
+ reg = <0>;
+ data-lanes = <1 3>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ mipi_in_cam1: endpoint@0 {
+ reg = <1>;
+ data-lanes = <1 3>;
+ };
+ };
+ };
+ }
This patch adds the DT binding documentation for the sensor interface module in Mediatek SoCs. Signed-off-by: Louis Kuo <louis.kuo@mediatek.com> --- .../devicetree/bindings/media/mediatek-seninf.txt | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek-seninf.txt