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Received: from mailgw02.mediatek.com ([216.200.240.185]) by casper.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hGKQQ-0002lY-SC; Tue, 16 Apr 2019 09:30:48 +0000 X-UUID: ebaf0d6952f74fe4a905f674a42bfcd3-20190416 X-UUID: ebaf0d6952f74fe4a905f674a42bfcd3-20190416 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 629456991; Tue, 16 Apr 2019 01:30:27 -0800 Received: from mtkmbs03n2.mediatek.inc (172.21.101.182) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 16 Apr 2019 02:30:26 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 16 Apr 2019 17:30:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 16 Apr 2019 17:30:18 +0800 From: Stu Hsieh To: Mauro Carvalho Chehab , Rob Herring , CK Hu Subject: [PATCH v2 08/15] [media] mtk-mipicsi: enable/disable ana clk Date: Tue, 16 Apr 2019 17:30:08 +0800 Message-ID: <1555407015-18130-9-git-send-email-stu.hsieh@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1555407015-18130-1-git-send-email-stu.hsieh@mediatek.com> References: <1555407015-18130-1-git-send-email-stu.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 8248653BC848B32118B6C6517FF036FC096F692F9EBA1E990BDAF7324736F1BC2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190416_103047_204240_EF0CFEDA X-CRM114-Status: GOOD ( 14.01 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Stu Hsieh , Matthias Brugger , linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch enable/disable ana clk when power on/off Signed-off-by: Stu Hsieh --- .../media/platform/mtk-mipicsi/mtk_mipicsi.c | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c index c92ffe6684ef..8a4079f0ed9b 100644 --- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c +++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c @@ -163,6 +163,41 @@ struct mtk_mipicsi_dev { V4L2_MBUS_PCLK_SAMPLE_FALLING | \ V4L2_MBUS_DATA_ACTIVE_HIGH) +static void mtk_mipicsi_ana_clk_enable(void __iomem *base, bool enable) +{ + if (enable) { + writel(1UL | readl(base + MIPI_RX_ANA00_CSI), + base + MIPI_RX_ANA00_CSI); + writel(1UL | readl(base + MIPI_RX_ANA04_CSI), + base + MIPI_RX_ANA04_CSI); + writel(1UL | readl(base + MIPI_RX_ANA08_CSI), + base + MIPI_RX_ANA08_CSI); + writel(1UL | readl(base + MIPI_RX_ANA0C_CSI), + base + MIPI_RX_ANA0C_CSI); + writel(1UL | readl(base + MIPI_RX_ANA10_CSI), + base + MIPI_RX_ANA10_CSI); + writel(1UL | readl(base + MIPI_RX_ANA20_CSI), + base + MIPI_RX_ANA20_CSI); + writel(1UL | readl(base + MIPI_RX_ANA24_CSI), + base + MIPI_RX_ANA24_CSI); + } else { + writel(~1UL & readl(base + MIPI_RX_ANA00_CSI), + base + MIPI_RX_ANA00_CSI); + writel(~1UL & readl(base + MIPI_RX_ANA04_CSI), + base + MIPI_RX_ANA04_CSI); + writel(~1UL & readl(base + MIPI_RX_ANA08_CSI), + base + MIPI_RX_ANA08_CSI); + writel(~1UL & readl(base + MIPI_RX_ANA0C_CSI), + base + MIPI_RX_ANA0C_CSI); + writel(~1UL & readl(base + MIPI_RX_ANA10_CSI), + base + MIPI_RX_ANA10_CSI); + writel(~1UL & readl(base + MIPI_RX_ANA20_CSI), + base + MIPI_RX_ANA20_CSI); + writel(~1UL & readl(base + MIPI_RX_ANA24_CSI), + base + MIPI_RX_ANA24_CSI); + } +} + static int get_subdev_register(const struct soc_camera_device *icd, struct v4l2_dbg_register *reg) { @@ -796,6 +831,8 @@ static int mtk_mipicsi_pm_suspend(struct device *dev) for (i = 0; i < mipicsi->clk_num; ++i) clk_disable_unprepare(mipicsi->clk[i]); + mtk_mipicsi_ana_clk_enable(mipicsi->ana, false); + if (mipicsi->larb_pdev != NULL) mtk_smi_larb_put(mipicsi->larb_pdev); @@ -833,6 +870,8 @@ static int mtk_mipicsi_pm_resume(struct device *dev) return ret; } + mtk_mipicsi_ana_clk_enable(mipicsi->ana, true); + /* enable digtal clock */ for (i = 0; i < mipicsi->clk_num; ++i) (void)clk_prepare_enable(mipicsi->clk[i]);