From patchwork Mon Apr 29 11:17:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 10921675 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 20DC314DB for ; Mon, 29 Apr 2019 11:18:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0C48D27CF3 for ; Mon, 29 Apr 2019 11:18:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 009302873E; Mon, 29 Apr 2019 11:18:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1313427CF3 for ; Mon, 29 Apr 2019 11:18:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ox2UWHrR8gU/2MhoDyOkz/KTO0uWUq3s4tWQJxYGTFA=; b=p+REQqi5u5M7dB Ax7JJi1Bo1vREWZwBy4+C2pF0pItLM06/2WFmVDpyjKmvGREgSnuTUDmfvWsFugiu4dvhgVpOqQgu HTiU92sgZu+wekmZd/SyLIkd7UQvKyDCxAK0VZ9ofHN+8c5Wd928gEzUYMeMBEuYfW4Ga5GidLaDs tovRxNtSEq6OIZf/iRFakjUaCrycn5YUKwBfQa2wVhD/EAeP6HUo2aInbbIp0VbPdJ75K5AMI4TVx 7U3D1UuLPKwSumDHELPIL/QbKcJSk016gNwYIoWfzr5S7VhdNV2TQEUXl4oyJgHP7FHsS7YnC+7Ez hwixM+vIoxFoB3PQq//g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hL4Id-0004q3-Kz; Mon, 29 Apr 2019 11:18:19 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hL4Ia-0004pe-FB for linux-mediatek@lists.infradead.org; Mon, 29 Apr 2019 11:18:18 +0000 X-UUID: 82c1be59e4484b348b7bac2e58044e3e-20190429 X-UUID: 82c1be59e4484b348b7bac2e58044e3e-20190429 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 612307392; Mon, 29 Apr 2019 03:18:09 -0800 Received: from MTKMBS02N2.mediatek.inc (172.21.101.101) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 29 Apr 2019 04:18:08 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 29 Apr 2019 19:18:04 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 29 Apr 2019 19:18:05 +0800 From: Andrew-sh.Cheng To: Rob Herring , Mark Rutland , Subject: [PATCH] Add cpufreq DTS node to the mt8183 and mt8183-evb. Date: Mon, 29 Apr 2019 19:17:54 +0800 Message-ID: <1556536674-27068-2-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1556536674-27068-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1556536674-27068-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: B72C95D1A3F7B3D8A272F85F25272DBF0B3CB2E52D02CEFFD46086ED8B9D8B0F2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190429_041816_509950_2F306B48 X-CRM114-Status: UNSURE ( 7.40 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-mediatek@lists.infradead.org, "Andrew-sh.Cheng" , srv_heupstream@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Andrew-sh.Cheng" Feature: cpufreq Signed-off-by: Andrew-sh.Cheng --- This patch is based on v5.1-rc1 and these patches: https://patchwork.kernel.org/patch/10893519/ --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 35 ++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 244 ++++++++++++++++++++++++++++ 2 files changed, 279 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 465cdab..b8057fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -175,6 +175,41 @@ }; }; +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu0 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu1 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu2 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu3 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu4 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu5 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu6 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu7 { + proc-supply = <&mt6358_vproc11_reg>; +}; &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index b36e37f..78d1ccf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -15,6 +15,218 @@ interrupt-parent = <&sysirq>; #address-cells = <2>; #size-cells = <2>; + cluster0_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <650000>; + }; + opp01 { + opp-hz = /bits/ 64 <910000000>; + opp-microvolt = <675000>; + }; + opp02 { + opp-hz = /bits/ 64 <1014000000>; + opp-microvolt = <700000>; + }; + opp03 { + opp-hz = /bits/ 64 <1131000000>; + opp-microvolt = <725000>; + }; + opp04 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <750000>; + }; + opp05 { + opp-hz = /bits/ 64 <1326000000>; + opp-microvolt = <775000>; + }; + opp06 { + opp-hz = /bits/ 64 <1417000000>; + opp-microvolt = <800000>; + }; + opp07 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <825000>; + }; + opp08 { + opp-hz = /bits/ 64 <1586000000>; + opp-microvolt = <850000>; + }; + opp09 { + opp-hz = /bits/ 64 <1625000000>; + opp-microvolt = <862500>; + }; + opp10 { + opp-hz = /bits/ 64 <1677000000>; + opp-microvolt = <881250>; + }; + opp11 { + opp-hz = /bits/ 64 <1716000000>; + opp-microvolt = <900000>; + }; + opp12 { + opp-hz = /bits/ 64 <1781000000>; + opp-microvolt = <925000>; + }; + opp13 { + opp-hz = /bits/ 64 <1846000000>; + opp-microvolt = <950000>; + }; + opp14 { + opp-hz = /bits/ 64 <1924000000>; + opp-microvolt = <975000>; + }; + opp15 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1000000>; + }; }; + + cluster1_opp: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <650000>; + }; + opp01 { + opp-hz = /bits/ 64 <910000000>; + opp-microvolt = <675000>; + }; + opp02 { + opp-hz = /bits/ 64 <1014000000>; + opp-microvolt = <700000>; + }; + opp03 { + opp-hz = /bits/ 64 <1131000000>; + opp-microvolt = <725000>; + }; + opp04 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <750000>; + }; + opp05 { + opp-hz = /bits/ 64 <1326000000>; + opp-microvolt = <775000>; + }; + opp06 { + opp-hz = /bits/ 64 <1417000000>; + opp-microvolt = <800000>; + }; + opp07 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <825000>; + }; + opp08 { + opp-hz = /bits/ 64 <1586000000>; + opp-microvolt = <850000>; + }; + opp09 { + opp-hz = /bits/ 64 <1625000000>; + opp-microvolt = <862500>; + }; + opp10 { + opp-hz = /bits/ 64 <1677000000>; + opp-microvolt = <881250>; + }; + opp11 { + opp-hz = /bits/ 64 <1716000000>; + opp-microvolt = <900000>; + }; + opp12 { + opp-hz = /bits/ 64 <1781000000>; + opp-microvolt = <925000>; + }; + opp13 { + opp-hz = /bits/ 64 <1846000000>; + opp-microvolt = <950000>; + }; + opp14 { + opp-hz = /bits/ 64 <1924000000>; + opp-microvolt = <975000>; + }; + opp15 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1000000>; + }; + }; + + cluster2_opp: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <273000000>; + opp-microvolt = <650000>; + }; + opp01 { + opp-hz = /bits/ 64 <338000000>; + opp-microvolt = <675000>; + }; + opp02 { + opp-hz = /bits/ 64 <403000000>; + opp-microvolt = <700000>; + }; + opp03 { + opp-hz = /bits/ 64 <463000000>; + opp-microvolt = <725000>; + }; + opp04 { + opp-hz = /bits/ 64 <546000000>; + opp-microvolt = <750000>; + }; + opp05 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <775000>; + }; + opp06 { + opp-hz = /bits/ 64 <689000000>; + opp-microvolt = <800000>; + }; + opp07 { + opp-hz = /bits/ 64 <767000000>; + opp-microvolt = <825000>; + }; + opp08 { + opp-hz = /bits/ 64 <845000000>; + opp-microvolt = <850000>; + }; + opp09 { + opp-hz = /bits/ 64 <871000000>; + opp-microvolt = <862500>; + }; + opp10 { + opp-hz = /bits/ 64 <923000000>; + opp-microvolt = <881250>; + }; + opp11 { + opp-hz = /bits/ 64 <962000000>; + opp-microvolt = <900000>; + }; + opp12 { + opp-hz = /bits/ 64 <1027000000>; + opp-microvolt = <925000>; + }; + opp13 { + opp-hz = /bits/ 64 <1092000000>; + opp-microvolt = <950000>; + }; + opp14 { + opp-hz = /bits/ 64 <1144000000>; + opp-microvolt = <975000>; + }; + opp15 { + opp-hz = /bits/ 64 <1196000000>; + opp-microvolt = <1000000>; + }; + }; + + cci: cci { + compatible = "mediatek,mt8183-cci"; + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>; + clock-names = "cci_clock"; + operating-points-v2 = <&cluster2_opp>; + }; cpus { #address-cells = <1>; @@ -57,6 +269,10 @@ compatible = "arm,cortex-a53"; reg = <0x000>; enable-method = "psci"; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { @@ -64,6 +280,10 @@ compatible = "arm,cortex-a53"; reg = <0x001>; enable-method = "psci"; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@2 { @@ -71,6 +291,10 @@ compatible = "arm,cortex-a53"; reg = <0x002>; enable-method = "psci"; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@3 { @@ -78,6 +302,10 @@ compatible = "arm,cortex-a53"; reg = <0x003>; enable-method = "psci"; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu4: cpu@100 { @@ -85,6 +313,10 @@ compatible = "arm,cortex-a73"; reg = <0x100>; enable-method = "psci"; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; }; cpu5: cpu@101 { @@ -92,6 +324,10 @@ compatible = "arm,cortex-a73"; reg = <0x101>; enable-method = "psci"; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; }; cpu6: cpu@102 { @@ -99,6 +335,10 @@ compatible = "arm,cortex-a73"; reg = <0x102>; enable-method = "psci"; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; }; cpu7: cpu@103 { @@ -106,6 +346,10 @@ compatible = "arm,cortex-a73"; reg = <0x103>; enable-method = "psci"; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; }; };