| Message ID | 1573616362-2557-3-git-send-email-ming-fan.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1,1/2] dt-bindings: mediatek: Add binding for MT6779 SMI | expand |
On Wed, 2019-11-13 at 11:39 +0800, Ming-Fan Chen wrote: > SMI bandwidth initial golden setting for MT6779 make sure > better performance of memory control for multimedia modules. I think this patch should be splitted to two, one adds the basic mt6779 support and config_port which should be a part of IOMMU. the other adds the bandwidth control support. > > Signed-off-by: Ming-Fan Chen <ming-fan.chen@mediatek.com> > --- > drivers/memory/mtk-smi.c | 141 +++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 139 insertions(+), 2 deletions(-) > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > index 439d7d8..f3618d0 100644 > --- a/drivers/memory/mtk-smi.c > +++ b/drivers/memory/mtk-smi.c > @@ -41,21 +41,50 @@ > #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) > #define F_MMU_EN BIT(0) > > +#define SMI_LARB_CMD_THRT_CON 0x24 > +#define SMI_LARB_SW_FLAG 0x40 > +#define SMI_LARB_WRR_PORT 0x100 > +#define SMI_LARB_WRR_PORTx(id) (SMI_LARB_WRR_PORT + (((id) & 0x1f) << 2)) The two WRR are not used. Remove. > +#define SMI_LARB_OSTDL_PORT 0x200 > +#define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) > + > /* SMI COMMON */ > +#define SMI_L1LEN 0x100 > +#define SMI_L1ARB0 0x104 > +#define SMI_L1ARB(id) (SMI_L1ARB0 + (((id) & 0x7) << 2)) > + > #define SMI_BUS_SEL 0x220 > #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) > /* All are MMU0 defaultly. Only specialize mmu1 here. */ > #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) > > +#define SMI_M4U_TH 0x234 > +#define SMI_FIFO_TH1 0x238 > +#define SMI_FIFO_TH2 0x23c > +#define SMI_DCM 0x300 > +#define SMI_DUMMY 0x444 > + > +#define SMI_LARB_PORT_NR_MAX 32 > +#define SMI_COMMON_LARB_NR_MAX 8 > +#define SMI_LARB_MISC_NR 2 > +#define SMI_COMMON_MISC_NR 6 > + > enum mtk_smi_gen { > MTK_SMI_GEN1, > MTK_SMI_GEN2 > }; > > +struct mtk_smi_reg_pair { > + u16 offset; > + u32 value; > +}; > + > struct mtk_smi_common_plat { > enum mtk_smi_gen gen; > bool has_gals; > u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ > + u16 *bwl; > + struct mtk_smi_reg_pair *misc; > }; > > struct mtk_smi_larb_gen { > @@ -63,6 +92,8 @@ struct mtk_smi_larb_gen { > void (*config_port)(struct device *); > unsigned int larb_direct_to_common_mask; > bool has_gals; > + u8 *bwl; Below you assign mtk_smi_larb_mt6779_bwl to this, it is: static u8 mtk_smi_larb_mt6779_bwl[MTK_LARB_NR_MAX][SMI_LARB_PORT_NR_MAX] then, is "u8 **" better? > + struct mtk_smi_reg_pair *misc; ditto, use **? > }; > > struct mtk_smi { > @@ -160,7 +191,7 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > { > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > u32 reg; > - int i; > + int i, id; > > if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > return; > @@ -170,6 +201,20 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > reg |= F_MMU_EN; > writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); > } > + > + if (larb->larb_gen->bwl) > + for (i = 0; i < larb->larb_gen->port_in_larb[larb->larbid]; i++) > + writel_relaxed(larb->larb_gen->bwl[larb->larbid * > + SMI_LARB_PORT_NR_MAX + i], > + larb->base + SMI_LARB_OSTDL_PORTx(i)); From this register name, I guess the name "bwl"(bandwidth limiter?) is not so good. Maybe it should be called by "osdl". At least, you should add a comment for this. like : u8 *bwl; /* for OSDL */ As below comment, If we don't have port_in_larb, always use 32 here, is it OK? (writing 0 for the non-exist port). > + > + if (larb->larb_gen->misc) > + for (i = 0, id = larb->larbid * SMI_LARB_MISC_NR; > + i < SMI_LARB_MISC_NR; i++, id++) > + writel_relaxed(larb->larb_gen->misc[id].value, > + larb->base + > + larb->larb_gen->misc[id].offset); There are 3 intention, It's not easy to read. A not-strong suggestion: we could add a new variable like has_bwc for mt6779 which have this bandwidth initial setting. And use "u8 **" for bwl. then the code will be like below: struct mtk_smi_reg_pair *misc; u8 *bwl; if (!larb->larb_gen->has_bwc) return; for (i = 0, bwl = larb->larb_gen->bwl[larb->larbid]; i < larb->larb_gen->port_in_larb[larb->larbid]; i++) writel_relaxed(bwl[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); for (i = 0,misc =larb->larb_gen->misc[larb->larbid]; i < SMI_LARB_MISC_NR; i++) writel_relaxed(misc[i].value, larb->base + misc[i].offset); the writel_relaxed can be finished in one line. > + wmb(); /* make sure settings are written */ > } > > static void mtk_smi_larb_config_port_mt8173(struct device *dev) > @@ -246,6 +291,55 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev) > /* IPU0 | IPU1 | CCU */ > }; > > +static u8 mtk_smi_larb_mt6779_bwl[MTK_LARB_NR_MAX][SMI_LARB_PORT_NR_MAX] = { Add const. Here the larb number in this SoC isn't MTK_LARB_NR_MAX(16). May be you could use: static const u8 mtk_smi_larb_mt6779_bwl[][SMI_LARB_PORT_NR_MAX] > + {0x28, 0x28, 0x01, 0x28, 0x01, 0x01, 0x0a, 0x0a, 0x28,}, > + {0x28, 0x01, 0x28, 0x28, 0x0a, 0x01, 0x01, 0x0d, 0x0d, 0x07, > + 0x01, 0x07, 0x01, 0x28,}, > + {0x18, 0x01, 0x08, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, > + 0x01, 0x01}, > + {0x01, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01, 0x04, 0x02, 0x01, > + 0x04, 0x01, 0x01, 0x01, 0x01, 0x04, 0x0b, 0x13, 0x14,}, > + {}, > + {0x13, 0x0f, 0x0d, 0x07, 0x07, 0x04, 0x03, 0x01, 0x03, 0x01, > + 0x05, 0x0c, 0x01, 0x01, 0x08, 0x06, 0x02, 0x01, 0x08, 0x08, > + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,}, > + {0x01, 0x01, 0x01,}, > + {0x01, 0x01, 0x01, 0x01,}, > + {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,}, > + {0x1f, 0x1a, 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x1f, 0x04, > + 0x04, 0x01, 0x01, 0x01, 0x02, 0x02, 0x04, 0x02, 0x01, 0x02, > + 0x04, 0x02, 0x02, 0x01,}, > + {0x1f, 0x1a, 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x1f, 0x1a, > + 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x01, 0x02, 0x02, 0x04, > + 0x02, 0x0a, 0x02, 0x02, 0x04, 0x02, 0x0a, 0x02, 0x04, 0x02, 0x04,}, > + {0x01, 0x01, 0x01, 0x01, 0x01,}, > +}; > + > +static struct mtk_smi_reg_pair const > + mtk_smi_larb_mt6779_misc[MTK_LARB_NR_MAX][SMI_LARB_MISC_NR] = { > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {}, > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > +}; > + > +static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { Move the mt6779 definition before mt8183. > + .port_in_larb = {9, 14, 12, 19, 0, 26, 3, 4, 10, 24, 31, 5,}, In mt2701, port_in_larb[n] is port_offset[n-1] + port_number[n-1]. It is not same with yours. Maybe your definition is better, But If you change it, please also change the mt2701. Make sure the meaning of port_in_larb are the same. > + .config_port = mtk_smi_larb_config_port_gen2_general, > + .larb_direct_to_common_mask = > + BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), > + /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ > + .bwl = (u8 *)mtk_smi_larb_mt6779_bwl, As above, here should be (u8 **). > + .misc = (struct mtk_smi_reg_pair *)mtk_smi_larb_mt6779_misc, > +}; > + > static const struct of_device_id mtk_smi_larb_of_ids[] = { > { > .compatible = "mediatek,mt8173-smi-larb", > @@ -260,6 +354,10 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev) > .data = &mtk_smi_larb_mt2712 > }, > { > + .compatible = "mediatek,mt6779-smi-larb", > + .data = &mtk_smi_larb_mt6779 > + }, > + { > .compatible = "mediatek,mt8183-smi-larb", > .data = &mtk_smi_larb_mt8183 > }, > @@ -393,6 +491,29 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) > F_MMU1_LARB(7), > }; > > +static u16 mtk_smi_common_mt6779_bwl[SMI_COMMON_LARB_NR_MAX] = { const. This bwl smi-common setting always have 8 register? Will it be changed? How about below?: static u16 mtk_smi_common_mt6779_bwl[] = { Add a new variable in struct mtk_smi_common_plat. larb_nr = ARRAY_SIZE(mtk_smi_common_mt6779_bwl) > + 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, > +}; > + > +static struct mtk_smi_reg_pair const > + mtk_smi_common_mt6779_misc[SMI_COMMON_MISC_NR] = { The tab in this line is unnecessary. > + {SMI_L1LEN, 0xb}, > + {SMI_M4U_TH, 0xe100e10}, > + {SMI_FIFO_TH1, 0x506090a}, > + {SMI_FIFO_TH2, 0x506090a}, > + {SMI_DCM, 0x4f1}, > + {SMI_DUMMY, 0x1}, Do all the settings above(including smi-larb) may be changed dynamically in different scenario? or all the setting only be set once? > +}; > + > +static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { ditto. Move the mt6779 definition before mt8183. > + .gen = MTK_SMI_GEN2, > + .has_gals = true, If you also have has_gals, Please update the binding. > + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | > + F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), > + .bwl = mtk_smi_common_mt6779_bwl, > + .misc = mtk_smi_common_mt6779_misc, > +}; > + > static const struct of_device_id mtk_smi_common_of_ids[] = { > { > .compatible = "mediatek,mt8173-smi-common", > @@ -407,6 +528,10 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) > .data = &mtk_smi_common_gen2, > }, > { > + .compatible = "mediatek,mt6779-smi-common", > + .data = &mtk_smi_common_mt6779, > + }, > + { > .compatible = "mediatek,mt8183-smi-common", > .data = &mtk_smi_common_mt8183, > }, > @@ -484,7 +609,7 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev) > { > struct mtk_smi *common = dev_get_drvdata(dev); > u32 bus_sel = common->plat->bus_sel; > - int ret; > + int i, ret; > > ret = mtk_smi_clk_enable(common); > if (ret) { > @@ -494,6 +619,18 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev) > > if (common->plat->gen == MTK_SMI_GEN2 && bus_sel) > writel(bus_sel, common->base + SMI_BUS_SEL); SMI_BUS_SEL looks can be a register in your common->plat->misc. This should be done in another patch. > + > + if (common->plat->bwl) > + for (i = 0; i < SMI_COMMON_LARB_NR_MAX; i++) > + writel_relaxed(common->plat->bwl[i], > + common->base + SMI_L1ARB(i)); From the register name, the "bwl" also is not so good. add a comment or rename it like "l1arb"? > + > + if (common->plat->misc) > + for (i = 0; i < SMI_COMMON_MISC_NR; i++) > + writel_relaxed(common->plat->misc[i].value, > + common->base + > + common->plat->misc[i].offset); > + wmb(); /* make sure settings are written */ > return 0; > } >
Dear Yong, Thanks for your comments and advice. Most of them I would like to add/modify in next version. On Fri, 2019-11-22 at 18:55 +0800, Yong Wu wrote: > On Wed, 2019-11-13 at 11:39 +0800, Ming-Fan Chen wrote: > > SMI bandwidth initial golden setting for MT6779 make sure > > better performance of memory control for multimedia modules. > > I think this patch should be splitted to two, one adds the basic mt6779 > support and config_port which should be a part of IOMMU. the other adds > the bandwidth control support. > > > > > Signed-off-by: Ming-Fan Chen <ming-fan.chen@mediatek.com> > > --- > > drivers/memory/mtk-smi.c | 141 +++++++++++++++++++++++++++++++++++++++++++++- > > 1 file changed, 139 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > > index 439d7d8..f3618d0 100644 > > --- a/drivers/memory/mtk-smi.c > > +++ b/drivers/memory/mtk-smi.c > > @@ -41,21 +41,50 @@ > > #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) > > #define F_MMU_EN BIT(0) > > > > +#define SMI_LARB_CMD_THRT_CON 0x24 > > +#define SMI_LARB_SW_FLAG 0x40 > > +#define SMI_LARB_WRR_PORT 0x100 > > +#define SMI_LARB_WRR_PORTx(id) (SMI_LARB_WRR_PORT + (((id) & 0x1f) << 2)) > > The two WRR are not used. Remove. > > > +#define SMI_LARB_OSTDL_PORT 0x200 > > +#define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) > > + > > /* SMI COMMON */ > > +#define SMI_L1LEN 0x100 > > +#define SMI_L1ARB0 0x104 > > +#define SMI_L1ARB(id) (SMI_L1ARB0 + (((id) & 0x7) << 2)) > > + > > #define SMI_BUS_SEL 0x220 > > #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) > > /* All are MMU0 defaultly. Only specialize mmu1 here. */ > > #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) > > > > +#define SMI_M4U_TH 0x234 > > +#define SMI_FIFO_TH1 0x238 > > +#define SMI_FIFO_TH2 0x23c > > +#define SMI_DCM 0x300 > > +#define SMI_DUMMY 0x444 > > + > > +#define SMI_LARB_PORT_NR_MAX 32 > > +#define SMI_COMMON_LARB_NR_MAX 8 > > +#define SMI_LARB_MISC_NR 2 > > +#define SMI_COMMON_MISC_NR 6 > > + > > enum mtk_smi_gen { > > MTK_SMI_GEN1, > > MTK_SMI_GEN2 > > }; > > > > +struct mtk_smi_reg_pair { > > + u16 offset; > > + u32 value; > > +}; > > + > > struct mtk_smi_common_plat { > > enum mtk_smi_gen gen; > > bool has_gals; > > u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ > > + u16 *bwl; > > + struct mtk_smi_reg_pair *misc; > > }; > > > > struct mtk_smi_larb_gen { > > @@ -63,6 +92,8 @@ struct mtk_smi_larb_gen { > > void (*config_port)(struct device *); > > unsigned int larb_direct_to_common_mask; > > bool has_gals; > > + u8 *bwl; > > Below you assign mtk_smi_larb_mt6779_bwl to this, it is: > static u8 mtk_smi_larb_mt6779_bwl[MTK_LARB_NR_MAX][SMI_LARB_PORT_NR_MAX] > > then, is "u8 **" better? > > > + struct mtk_smi_reg_pair *misc; > > ditto, use **? > > > }; > > > > struct mtk_smi { > > @@ -160,7 +191,7 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > { > > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > u32 reg; > > - int i; > > + int i, id; > > > > if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > > return; > > @@ -170,6 +201,20 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > reg |= F_MMU_EN; > > writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); > > } > > + > > + if (larb->larb_gen->bwl) > > + for (i = 0; i < larb->larb_gen->port_in_larb[larb->larbid]; i++) > > + writel_relaxed(larb->larb_gen->bwl[larb->larbid * > > + SMI_LARB_PORT_NR_MAX + i], > > + larb->base + SMI_LARB_OSTDL_PORTx(i)); > > From this register name, I guess the name "bwl"(bandwidth limiter?) is > not so good. Maybe it should be called by "osdl". At least, you should > add a comment for this. like : u8 *bwl; /* for OSDL */ > > As below comment, If we don't have port_in_larb, always use 32 here, is > it OK? (writing 0 for the non-exist port). > > > + > > + if (larb->larb_gen->misc) > > + for (i = 0, id = larb->larbid * SMI_LARB_MISC_NR; > > + i < SMI_LARB_MISC_NR; i++, id++) > > + writel_relaxed(larb->larb_gen->misc[id].value, > > + larb->base + > > + larb->larb_gen->misc[id].offset); > > There are 3 intention, It's not easy to read. A not-strong suggestion: > we could add a new variable like has_bwc for mt6779 which have this > bandwidth initial setting. And use "u8 **" for bwl. then the code will > be like below: > > struct mtk_smi_reg_pair *misc; > u8 *bwl; > > if (!larb->larb_gen->has_bwc) > return; > > for (i = 0, bwl = larb->larb_gen->bwl[larb->larbid]; > i < larb->larb_gen->port_in_larb[larb->larbid]; i++) > writel_relaxed(bwl[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); > > for (i = 0,misc =larb->larb_gen->misc[larb->larbid]; > i < SMI_LARB_MISC_NR; i++) > writel_relaxed(misc[i].value, larb->base + misc[i].offset); > > the writel_relaxed can be finished in one line. > Using "u8 **" will not be the same as we expected. Because "u8 **" replys a pointer which points to a pointer. bwl[0] here will become 0xa0a01012801012828 by mtk_smi_larb_mt6779_bwl[0] = {0x28, 0x28, 0x01, 0x28, 0x01, 0x01, 0x0a, 0x0a, ...} in little endian format. If single pointer is not acceptable, there is another way as follows: /* definition */ struct mtk_smi_larb_gen { const u8 (*bwl)[SMI_LARB_PORT_NR_MAX]; }; /* initialization */ static const u8 mtk_smi_larb_mt6779_bwl[][SMI_LARB_PORT_NR_MAX] = { ... }; static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { .bwl = mtk_smi_larb_mt6779_bwl, }; /* implementation */ const u8 *bwl; for (i = 0, bwl = larb->larb_gen->bwl[larb->larbid]; i < larb->larb_gen->port_in_larb[larb->larbid]; i++) writel_relaxed(bwl[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); Will this be okay with you? > > > + wmb(); /* make sure settings are written */ > > } > > > > static void mtk_smi_larb_config_port_mt8173(struct device *dev) > > @@ -246,6 +291,55 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev) > > /* IPU0 | IPU1 | CCU */ > > }; > > > > +static u8 mtk_smi_larb_mt6779_bwl[MTK_LARB_NR_MAX][SMI_LARB_PORT_NR_MAX] = { > > Add const. > > Here the larb number in this SoC isn't MTK_LARB_NR_MAX(16). May be you > could use: > static const u8 mtk_smi_larb_mt6779_bwl[][SMI_LARB_PORT_NR_MAX] > > > + {0x28, 0x28, 0x01, 0x28, 0x01, 0x01, 0x0a, 0x0a, 0x28,}, > > + {0x28, 0x01, 0x28, 0x28, 0x0a, 0x01, 0x01, 0x0d, 0x0d, 0x07, > > + 0x01, 0x07, 0x01, 0x28,}, > > + {0x18, 0x01, 0x08, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, > > + 0x01, 0x01}, > > + {0x01, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01, 0x04, 0x02, 0x01, > > + 0x04, 0x01, 0x01, 0x01, 0x01, 0x04, 0x0b, 0x13, 0x14,}, > > + {}, > > + {0x13, 0x0f, 0x0d, 0x07, 0x07, 0x04, 0x03, 0x01, 0x03, 0x01, > > + 0x05, 0x0c, 0x01, 0x01, 0x08, 0x06, 0x02, 0x01, 0x08, 0x08, > > + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,}, > > + {0x01, 0x01, 0x01,}, > > + {0x01, 0x01, 0x01, 0x01,}, > > + {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,}, > > + {0x1f, 0x1a, 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x1f, 0x04, > > + 0x04, 0x01, 0x01, 0x01, 0x02, 0x02, 0x04, 0x02, 0x01, 0x02, > > + 0x04, 0x02, 0x02, 0x01,}, > > + {0x1f, 0x1a, 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x1f, 0x1a, > > + 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x01, 0x02, 0x02, 0x04, > > + 0x02, 0x0a, 0x02, 0x02, 0x04, 0x02, 0x0a, 0x02, 0x04, 0x02, 0x04,}, > > + {0x01, 0x01, 0x01, 0x01, 0x01,}, > > +}; > > + > > +static struct mtk_smi_reg_pair > > const > > > + mtk_smi_larb_mt6779_misc[MTK_LARB_NR_MAX][SMI_LARB_MISC_NR] = { > > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > > + {}, > > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > > + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, > > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > > + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, > > +}; > > + > > +static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { > > Move the mt6779 definition before mt8183. > > > + .port_in_larb = {9, 14, 12, 19, 0, 26, 3, 4, 10, 24, 31, 5,}, > > In mt2701, port_in_larb[n] is port_offset[n-1] + port_number[n-1]. > It is not same with yours. > > Maybe your definition is better, But If you change it, please also > change the mt2701. Make sure the meaning of port_in_larb are the same. > > > + .config_port = mtk_smi_larb_config_port_gen2_general, > > + .larb_direct_to_common_mask = > > + BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), > > + /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ > > + .bwl = (u8 *)mtk_smi_larb_mt6779_bwl, > > As above, here should be (u8 **). > > > + .misc = (struct mtk_smi_reg_pair *)mtk_smi_larb_mt6779_misc, > > +}; > > + > > static const struct of_device_id mtk_smi_larb_of_ids[] = { > > { > > .compatible = "mediatek,mt8173-smi-larb", > > @@ -260,6 +354,10 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev) > > .data = &mtk_smi_larb_mt2712 > > }, > > { > > + .compatible = "mediatek,mt6779-smi-larb", > > + .data = &mtk_smi_larb_mt6779 > > + }, > > + { > > .compatible = "mediatek,mt8183-smi-larb", > > .data = &mtk_smi_larb_mt8183 > > }, > > @@ -393,6 +491,29 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) > > F_MMU1_LARB(7), > > }; > > > > +static u16 mtk_smi_common_mt6779_bwl[SMI_COMMON_LARB_NR_MAX] = { > > const. > > This bwl smi-common setting always have 8 register? Will it be changed? > > How about below?: > > static u16 mtk_smi_common_mt6779_bwl[] = { > > Add a new variable in struct mtk_smi_common_plat. > > larb_nr = ARRAY_SIZE(mtk_smi_common_mt6779_bwl) > > > + 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, > > +}; > > + > > +static struct mtk_smi_reg_pair > > const > > + mtk_smi_common_mt6779_misc[SMI_COMMON_MISC_NR] = { > > The tab in this line is unnecessary. > > > + {SMI_L1LEN, 0xb}, > > + {SMI_M4U_TH, 0xe100e10}, > > + {SMI_FIFO_TH1, 0x506090a}, > > + {SMI_FIFO_TH2, 0x506090a}, > > + {SMI_DCM, 0x4f1}, > > + {SMI_DUMMY, 0x1}, > > > Do all the settings above(including smi-larb) may be changed dynamically > in different scenario? or all the setting only be set once? > The setting will only be set once here. The dynamic part will be in another patch about bandwidth control support you have mentioned. > > +}; > > + > > +static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { > > ditto. Move the mt6779 definition before mt8183. > > > + .gen = MTK_SMI_GEN2, > > + .has_gals = true, > > If you also have has_gals, Please update the binding. > > > + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | > > + F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), > > + .bwl = mtk_smi_common_mt6779_bwl, > > + .misc = mtk_smi_common_mt6779_misc, > > +}; > > + > > static const struct of_device_id mtk_smi_common_of_ids[] = { > > { > > .compatible = "mediatek,mt8173-smi-common", > > @@ -407,6 +528,10 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) > > .data = &mtk_smi_common_gen2, > > }, > > { > > + .compatible = "mediatek,mt6779-smi-common", > > + .data = &mtk_smi_common_mt6779, > > + }, > > + { > > .compatible = "mediatek,mt8183-smi-common", > > .data = &mtk_smi_common_mt8183, > > }, > > @@ -484,7 +609,7 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev) > > { > > struct mtk_smi *common = dev_get_drvdata(dev); > > u32 bus_sel = common->plat->bus_sel; > > - int ret; > > + int i, ret; > > > > ret = mtk_smi_clk_enable(common); > > if (ret) { > > @@ -494,6 +619,18 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev) > > > > if (common->plat->gen == MTK_SMI_GEN2 && bus_sel) > > writel(bus_sel, common->base + SMI_BUS_SEL); > > SMI_BUS_SEL looks can be a register in your common->plat->misc. > This should be done in another patch. > > > + > > + if (common->plat->bwl) > > + for (i = 0; i < SMI_COMMON_LARB_NR_MAX; i++) > > + writel_relaxed(common->plat->bwl[i], > > + common->base + SMI_L1ARB(i)); > > From the register name, the "bwl" also is not so good. add a comment or > rename it like "l1arb"? > > > + > > + if (common->plat->misc) > > + for (i = 0; i < SMI_COMMON_MISC_NR; i++) > > + writel_relaxed(common->plat->misc[i].value, > > + common->base + > > + common->plat->misc[i].offset); > > + wmb(); /* make sure settings are written */ > > return 0; > > } > > > >
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index 439d7d8..f3618d0 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -41,21 +41,50 @@ #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) #define F_MMU_EN BIT(0) +#define SMI_LARB_CMD_THRT_CON 0x24 +#define SMI_LARB_SW_FLAG 0x40 +#define SMI_LARB_WRR_PORT 0x100 +#define SMI_LARB_WRR_PORTx(id) (SMI_LARB_WRR_PORT + (((id) & 0x1f) << 2)) +#define SMI_LARB_OSTDL_PORT 0x200 +#define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) + /* SMI COMMON */ +#define SMI_L1LEN 0x100 +#define SMI_L1ARB0 0x104 +#define SMI_L1ARB(id) (SMI_L1ARB0 + (((id) & 0x7) << 2)) + #define SMI_BUS_SEL 0x220 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) /* All are MMU0 defaultly. Only specialize mmu1 here. */ #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) +#define SMI_M4U_TH 0x234 +#define SMI_FIFO_TH1 0x238 +#define SMI_FIFO_TH2 0x23c +#define SMI_DCM 0x300 +#define SMI_DUMMY 0x444 + +#define SMI_LARB_PORT_NR_MAX 32 +#define SMI_COMMON_LARB_NR_MAX 8 +#define SMI_LARB_MISC_NR 2 +#define SMI_COMMON_MISC_NR 6 + enum mtk_smi_gen { MTK_SMI_GEN1, MTK_SMI_GEN2 }; +struct mtk_smi_reg_pair { + u16 offset; + u32 value; +}; + struct mtk_smi_common_plat { enum mtk_smi_gen gen; bool has_gals; u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ + u16 *bwl; + struct mtk_smi_reg_pair *misc; }; struct mtk_smi_larb_gen { @@ -63,6 +92,8 @@ struct mtk_smi_larb_gen { void (*config_port)(struct device *); unsigned int larb_direct_to_common_mask; bool has_gals; + u8 *bwl; + struct mtk_smi_reg_pair *misc; }; struct mtk_smi { @@ -160,7 +191,7 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) { struct mtk_smi_larb *larb = dev_get_drvdata(dev); u32 reg; - int i; + int i, id; if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) return; @@ -170,6 +201,20 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) reg |= F_MMU_EN; writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); } + + if (larb->larb_gen->bwl) + for (i = 0; i < larb->larb_gen->port_in_larb[larb->larbid]; i++) + writel_relaxed(larb->larb_gen->bwl[larb->larbid * + SMI_LARB_PORT_NR_MAX + i], + larb->base + SMI_LARB_OSTDL_PORTx(i)); + + if (larb->larb_gen->misc) + for (i = 0, id = larb->larbid * SMI_LARB_MISC_NR; + i < SMI_LARB_MISC_NR; i++, id++) + writel_relaxed(larb->larb_gen->misc[id].value, + larb->base + + larb->larb_gen->misc[id].offset); + wmb(); /* make sure settings are written */ } static void mtk_smi_larb_config_port_mt8173(struct device *dev) @@ -246,6 +291,55 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev) /* IPU0 | IPU1 | CCU */ }; +static u8 mtk_smi_larb_mt6779_bwl[MTK_LARB_NR_MAX][SMI_LARB_PORT_NR_MAX] = { + {0x28, 0x28, 0x01, 0x28, 0x01, 0x01, 0x0a, 0x0a, 0x28,}, + {0x28, 0x01, 0x28, 0x28, 0x0a, 0x01, 0x01, 0x0d, 0x0d, 0x07, + 0x01, 0x07, 0x01, 0x28,}, + {0x18, 0x01, 0x08, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, + 0x01, 0x01}, + {0x01, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01, 0x04, 0x02, 0x01, + 0x04, 0x01, 0x01, 0x01, 0x01, 0x04, 0x0b, 0x13, 0x14,}, + {}, + {0x13, 0x0f, 0x0d, 0x07, 0x07, 0x04, 0x03, 0x01, 0x03, 0x01, + 0x05, 0x0c, 0x01, 0x01, 0x08, 0x06, 0x02, 0x01, 0x08, 0x08, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,}, + {0x01, 0x01, 0x01,}, + {0x01, 0x01, 0x01, 0x01,}, + {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,}, + {0x1f, 0x1a, 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x1f, 0x04, + 0x04, 0x01, 0x01, 0x01, 0x02, 0x02, 0x04, 0x02, 0x01, 0x02, + 0x04, 0x02, 0x02, 0x01,}, + {0x1f, 0x1a, 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x1f, 0x1a, + 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x01, 0x02, 0x02, 0x04, + 0x02, 0x0a, 0x02, 0x02, 0x04, 0x02, 0x0a, 0x02, 0x04, 0x02, 0x04,}, + {0x01, 0x01, 0x01, 0x01, 0x01,}, +}; + +static struct mtk_smi_reg_pair + mtk_smi_larb_mt6779_misc[MTK_LARB_NR_MAX][SMI_LARB_MISC_NR] = { + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, + {}, + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, + {{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},}, +}; + +static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { + .port_in_larb = {9, 14, 12, 19, 0, 26, 3, 4, 10, 24, 31, 5,}, + .config_port = mtk_smi_larb_config_port_gen2_general, + .larb_direct_to_common_mask = + BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), + /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ + .bwl = (u8 *)mtk_smi_larb_mt6779_bwl, + .misc = (struct mtk_smi_reg_pair *)mtk_smi_larb_mt6779_misc, +}; + static const struct of_device_id mtk_smi_larb_of_ids[] = { { .compatible = "mediatek,mt8173-smi-larb", @@ -260,6 +354,10 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev) .data = &mtk_smi_larb_mt2712 }, { + .compatible = "mediatek,mt6779-smi-larb", + .data = &mtk_smi_larb_mt6779 + }, + { .compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183 }, @@ -393,6 +491,29 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) F_MMU1_LARB(7), }; +static u16 mtk_smi_common_mt6779_bwl[SMI_COMMON_LARB_NR_MAX] = { + 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, +}; + +static struct mtk_smi_reg_pair + mtk_smi_common_mt6779_misc[SMI_COMMON_MISC_NR] = { + {SMI_L1LEN, 0xb}, + {SMI_M4U_TH, 0xe100e10}, + {SMI_FIFO_TH1, 0x506090a}, + {SMI_FIFO_TH2, 0x506090a}, + {SMI_DCM, 0x4f1}, + {SMI_DUMMY, 0x1}, +}; + +static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { + .gen = MTK_SMI_GEN2, + .has_gals = true, + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | + F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), + .bwl = mtk_smi_common_mt6779_bwl, + .misc = mtk_smi_common_mt6779_misc, +}; + static const struct of_device_id mtk_smi_common_of_ids[] = { { .compatible = "mediatek,mt8173-smi-common", @@ -407,6 +528,10 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) .data = &mtk_smi_common_gen2, }, { + .compatible = "mediatek,mt6779-smi-common", + .data = &mtk_smi_common_mt6779, + }, + { .compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183, }, @@ -484,7 +609,7 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev) { struct mtk_smi *common = dev_get_drvdata(dev); u32 bus_sel = common->plat->bus_sel; - int ret; + int i, ret; ret = mtk_smi_clk_enable(common); if (ret) { @@ -494,6 +619,18 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev) if (common->plat->gen == MTK_SMI_GEN2 && bus_sel) writel(bus_sel, common->base + SMI_BUS_SEL); + + if (common->plat->bwl) + for (i = 0; i < SMI_COMMON_LARB_NR_MAX; i++) + writel_relaxed(common->plat->bwl[i], + common->base + SMI_L1ARB(i)); + + if (common->plat->misc) + for (i = 0; i < SMI_COMMON_MISC_NR; i++) + writel_relaxed(common->plat->misc[i].value, + common->base + + common->plat->misc[i].offset); + wmb(); /* make sure settings are written */ return 0; }
SMI bandwidth initial golden setting for MT6779 make sure better performance of memory control for multimedia modules. Signed-off-by: Ming-Fan Chen <ming-fan.chen@mediatek.com> --- drivers/memory/mtk-smi.c | 141 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 139 insertions(+), 2 deletions(-)