@@ -170,6 +170,10 @@ struct mtk_ddp {
struct mtk_mmsys_reg_data {
u32 ovl0_mout_en;
+ u32 rdma1_sout_sel_in;
+ u32 rdma1_sout_dpi0;
+ u32 dpi0_sel_in;
+ u32 dpi0_sel_in_rdma1;
};
static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -256,6 +260,10 @@ struct mtk_mmsys_reg_data {
const struct mtk_mmsys_reg_data mt8173_mmsys_reg_data = {
.ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
+ .rdma1_sout_sel_in = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN,
+ .rdma1_sout_dpi0 = RDMA1_SOUT_DPI0,
+ .dpi0_sel_in = DISP_REG_CONFIG_DPI_SEL_IN,
+ .dpi0_sel_in_rdma1 = DPI0_SEL_IN_RDMA1,
};
static unsigned int mtk_ddp_mout_en(const struct mtk_mmsys_reg_data *data,
@@ -311,8 +319,8 @@ static unsigned int mtk_ddp_mout_en(const struct mtk_mmsys_reg_data *data,
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI0;
+ *addr = data->rdma1_sout_sel_in;
+ value =data->rdma1_sout_dpi0;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DPI1;
@@ -349,8 +357,8 @@ static unsigned int mtk_ddp_sel_in(const struct mtk_mmsys_reg_data *data,
*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
value = COLOR0_SEL_IN_OVL0;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DPI_SEL_IN;
- value = DPI0_SEL_IN_RDMA1;
+ *addr = data->dpi0_sel_in;
+ value = data->dpi0_sel_in_rdma1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI1_SEL_IN_RDMA1;
the register offset and value will be different in future SOC, add private data for rdma1->dpi0 use case. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-)