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Thu, 06 Aug 2020 01:22:05 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Aug 2020 02:22:04 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Aug 2020 17:22:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Aug 2020 17:22:00 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer Subject: [PATCH v17 11/12] arm64: dts: Add power controller device node of MT8183 Date: Thu, 6 Aug 2020 17:21:54 +0800 Message-ID: <1596705715-15320-12-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> References: <1596705715-15320-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200806_052214_646091_F64F22DE X-CRM114-Status: GOOD ( 11.87 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Add power controller node and smi-common node for MT8183 In scpsys node, it contains clocks and regmapping of infracfg and smi-common for bus protection. And list all the power domains of MT8183 under scpsys node to show the dependency between each other through hierarchical structure. Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 123 +++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 1e03c84..4940bda 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "mt8183-pinfunc.h" @@ -309,6 +310,123 @@ #interrupt-cells = <2>; }; + scpsys: power-controller@10006000 { + compatible = "mediatek,mt8183-scpsys", "syscon"; + reg = <0 0x10006000 0 0x1000>; + clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_MUX_MFG>, + <&topckgen CLK_TOP_MUX_MM>, + <&topckgen CLK_TOP_MUX_CAM>, + <&topckgen CLK_TOP_MUX_IMG>, + <&topckgen CLK_TOP_MUX_IPU_IF>, + <&topckgen CLK_TOP_MUX_DSP>, + <&topckgen CLK_TOP_MUX_DSP1>, + <&topckgen CLK_TOP_MUX_DSP2>; + clock-names = "audio", "audio1", "audio2", "mfg", "mm", + "cam", "isp", "vpu", "vpu1", "vpu2", + "vpu3"; + infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + audio@MT8183_POWER_DOMAIN_AUDIO { + reg = ; + }; + + conn@MT8183_POWER_DOMAIN_CONN { + reg = ; + }; + + mfg_async@MT8183_POWER_DOMAIN_MFG_ASYNC { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + + mfg@MT8183_POWER_DOMAIN_MFG { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + + mfg_core0@MT8183_POWER_DOMAIN_MFG_CORE0 { + reg = ; + }; + + mfg_core1@MT8183_POWER_DOMAIN_MFG_CORE1 { + reg = ; + }; + + mfg_2d@MT8183_POWER_DOMAIN_MFG_2D { + reg = ; + }; + }; + }; + + disp@MT8183_POWER_DOMAIN_DISP { + reg = ; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB1>, + <&mmsys CLK_MM_GALS_COMM0>, + <&mmsys CLK_MM_GALS_COMM1>, + <&mmsys CLK_MM_GALS_CCU2MM>, + <&mmsys CLK_MM_GALS_IPU12MM>, + <&mmsys CLK_MM_GALS_IMG2MM>, + <&mmsys CLK_MM_GALS_CAM2MM>, + <&mmsys CLK_MM_GALS_IPU2MM>; + #address-cells = <1>; + #size-cells = <0>; + + cam@MT8183_POWER_DOMAIN_CAM { + reg = ; + clocks = <&camsys CLK_CAM_LARB6>, + <&camsys CLK_CAM_LARB3>, + <&camsys CLK_CAM_SENINF>, + <&camsys CLK_CAM_CAMSV0>, + <&camsys CLK_CAM_CAMSV1>, + <&camsys CLK_CAM_CAMSV2>, + <&camsys CLK_CAM_CCU>; + }; + + isp@MT8183_POWER_DOMAIN_ISP { + reg = ; + clocks = <&imgsys CLK_IMG_LARB5>, + <&imgsys CLK_IMG_LARB2>; + }; + + vdec@MT8183_POWER_DOMAIN_VDEC { + reg = ; + }; + + vden@MT8183_POWER_DOMAIN_VENC { + reg = ; + }; + + vpu_top@MT8183_POWER_DOMAIN_VPU_TOP { + reg = ; + clocks = <&ipu_conn CLK_IPU_CONN_IPU>, + <&ipu_conn CLK_IPU_CONN_AHB>, + <&ipu_conn CLK_IPU_CONN_AXI>, + <&ipu_conn CLK_IPU_CONN_ISP>, + <&ipu_conn CLK_IPU_CONN_CAM_ADL>, + <&ipu_conn CLK_IPU_CONN_IMG_ADL>; + #address-cells = <1>; + #size-cells = <0>; + + vpu_core0@MT8183_POWER_DOMAIN_VPU_CORE0 { + reg = ; + }; + + vpu_core1@MT8183_POWER_DOMAIN_VPU_CORE1 { + reg = ; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8183-wdt", "mediatek,mt6589-wdt"; @@ -690,6 +808,11 @@ #clock-cells = <1>; }; + smi_common: smi@14019000 { + compatible = "mediatek,mt8183-smi-common", "syscon"; + reg = <0 0x14019000 0 0x1000>; + }; + imgsys: syscon@15020000 { compatible = "mediatek,mt8183-imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>;