diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index 2bc3677..efe2025 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -15,8 +15,9 @@ power/power-domain.yaml. It provides the power domains defined in
 - include/dt-bindings/power/mt2701-power.h
 - include/dt-bindings/power/mt2712-power.h
 - include/dt-bindings/power/mt7622-power.h
+- include/dt-bindings/power/mt8183-power.h
 
-Required properties:
+Required properties for power controller:
 - compatible: Should be one of:
 	- "mediatek,mt2701-scpsys"
 	- "mediatek,mt2712-scpsys"
@@ -27,12 +28,15 @@ Required properties:
 	- "mediatek,mt7623a-scpsys": For MT7623A SoC
 	- "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
 	- "mediatek,mt8173-scpsys"
+	- "mediatek,mt8183-scpsys"
 - #power-domain-cells: Must be 1
+- #address-cells: Should be 1
+- #size-cells: Should be 0
 - reg: Address range of the SCPSYS unit
 - infracfg: must contain a phandle to the infracfg controller
-- clock, clock-names: clocks according to the common clock binding.
-                      These are clocks which hardware needs to be
-                      enabled before enabling certain power domains.
+- clocks, clock-names: clocks according to the common clock binding.
+                       These are clocks which hardware needs to be
+                       enabled before enabling certain power domains.
 	Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
 	Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
 	Required clocks for MT6765: MUX: "mm", "mfg"
@@ -43,8 +47,11 @@ Required properties:
 	Required clocks for MT7622 or MT7629: "hif_sel"
 	Required clocks for MT7623A: "ethif"
 	Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
+	Required clocks for MT8183: "audio", "audio1", "audio2", "mfg", "mm",
+				    "cam", "isp", "vpu", "vpu1", "vpu2",
+				    "vpu3";
 
-Optional properties:
+Optional properties for power controller:
 - vdec-supply: Power supply for the vdec power domain
 - venc-supply: Power supply for the venc power domain
 - isp-supply: Power supply for the isp power domain
@@ -55,6 +62,16 @@ Optional properties:
 - mfg_async-supply: Power supply for the mfg_async power domain
 - mfg_2d-supply: Power supply for the mfg_2d power domain
 - mfg-supply: Power supply for the mfg power domain
+- mediatek,smi : A phandle to the smi_common node
+
+Required properties for power domain sub nodes:
+- reg: index of the power domain, should use macros in:
+	"include/dt-bindings/power/mt8192-power.h" - for power domain of MT8192.
+
+Optional properties for power domain sub nodes:
+- clocks: clocks according to the common clock binding.
+          These are clocks which hardware needs to be enabled before
+          releasing the bus protection.
 
 Example:
 
@@ -70,6 +87,60 @@ Example:
 		clock-names = "mfg", "mm", "venc", "venc_lt";
 	};
 
+Example(power domain sub node within power controller):
+
+	scpsys: power-controller@10006000 {
+		compatible = "mediatek,mt8183-scpsys", "syscon";
+		reg = <0 0x10006000 0 0x1000>;
+		clocks = <&topckgen CLK_TOP_MUX_MM>,
+			 <&topckgen CLK_TOP_MUX_IPU_IF>,
+			 <&topckgen CLK_TOP_MUX_DSP>,
+			 <&topckgen CLK_TOP_MUX_DSP1>,
+			 <&topckgen CLK_TOP_MUX_DSP2>;
+		clock-names = "mm", "vpu", "vpu1", "vpu2", "vpu3";
+		infracfg = <&infracfg>;
+		mediatek,smi = <&smi_common>;
+		#power-domain-cells = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		conn@MT8183_POWER_DOMAIN_CONN {
+			reg = <MT8183_POWER_DOMAIN_CONN>;
+		};
+
+		disp@MT8183_POWER_DOMAIN_DISP {
+			reg = <MT8183_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_SMI_COMMON>,
+				 <&mmsys CLK_MM_SMI_LARB0>,
+				 <&mmsys CLK_MM_SMI_LARB1>,
+				 <&mmsys CLK_MM_GALS_COMM0>,
+				 <&mmsys CLK_MM_GALS_COMM1>,
+				 <&mmsys CLK_MM_GALS_CCU2MM>,
+				 <&mmsys CLK_MM_GALS_IPU12MM>,
+				 <&mmsys CLK_MM_GALS_IMG2MM>,
+				 <&mmsys CLK_MM_GALS_CAM2MM>,
+				 <&mmsys CLK_MM_GALS_IPU2MM>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			vpu_top@MT8183_POWER_DOMAIN_VPU_TOP {
+				reg = <MT8183_POWER_DOMAIN_VPU_TOP>;
+				clocks = <&ipu_conn CLK_IPU_CONN_IPU>,
+					 <&ipu_conn CLK_IPU_CONN_AHB>,
+					 <&ipu_conn CLK_IPU_CONN_AXI>,
+					 <&ipu_conn CLK_IPU_CONN_ISP>,
+					 <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
+					 <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				vpu_core0@MT8183_POWER_DOMAIN_VPU_CORE0 {
+					reg = <MT8183_POWER_DOMAIN_VPU_CORE0>;
+				};
+			};
+		};
+	};
+
 Example consumer:
 
 	afe: mt8173-afe-pcm@11220000 {
diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h
new file mode 100644
index 0000000..d1ab387
--- /dev/null
+++ b/include/dt-bindings/power/mt8183-power.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
+#define _DT_BINDINGS_POWER_MT8183_POWER_H
+
+#define MT8183_POWER_DOMAIN_AUDIO	0
+#define MT8183_POWER_DOMAIN_CONN	1
+#define MT8183_POWER_DOMAIN_MFG_ASYNC	2
+#define MT8183_POWER_DOMAIN_MFG		3
+#define MT8183_POWER_DOMAIN_MFG_CORE0	4
+#define MT8183_POWER_DOMAIN_MFG_CORE1	5
+#define MT8183_POWER_DOMAIN_MFG_2D	6
+#define MT8183_POWER_DOMAIN_DISP	7
+#define MT8183_POWER_DOMAIN_CAM		8
+#define MT8183_POWER_DOMAIN_ISP		9
+#define MT8183_POWER_DOMAIN_VDEC	10
+#define MT8183_POWER_DOMAIN_VENC	11
+#define MT8183_POWER_DOMAIN_VPU_TOP	12
+#define MT8183_POWER_DOMAIN_VPU_CORE0	13
+#define MT8183_POWER_DOMAIN_VPU_CORE1	14
+
+#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
