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Thu, 22 Oct 2020 04:47:57 -0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Oct 2020 05:47:41 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Oct 2020 20:47:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Oct 2020 20:47:39 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" Subject: [PATCH v2 4/4] arm64: dts: mediatek: Add mt8192 power domains controller Date: Thu, 22 Oct 2020 20:47:37 +0800 Message-ID: <1603370857-30646-5-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1603370857-30646-1-git-send-email-weiyi.lu@mediatek.com> References: <1603370857-30646-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201022_084830_620750_B44D39F2 X-CRM114-Status: GOOD ( 12.43 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Add power domains controller node for SoC mt8192 Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 201 +++++++++++++++++++++++++++++++ 1 file changed, 201 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index b3fab4f..9274291 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8192"; @@ -257,6 +258,206 @@ #interrupt-cells = <2>; }; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8192-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + audio@MT8192_POWER_DOMAIN_AUDIO { + reg = ; + clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_INFRA_AUDIO_26M_B>, + <&infracfg CLK_INFRA_AUDIO>; + clock-names = "audio", "audio1", "audio2"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + conn@MT8192_POWER_DOMAIN_CONN { + reg = ; + clocks = <&infracfg CLK_INFRA_PMIC_CONN>; + clock-names = "conn"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + mfg@MT8192_POWER_DOMAIN_MFG0 { + reg = ; + clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + mfg1@MT8192_POWER_DOMAIN_MFG1 { + reg = ; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + mfg2@MT8192_POWER_DOMAIN_MFG2 { + reg = ; + #power-domain-cells = <0>; + }; + + mfg3@MT8192_POWER_DOMAIN_MFG3 { + reg = ; + #power-domain-cells = <0>; + }; + + mfg4@MT8192_POWER_DOMAIN_MFG4 { + reg = ; + #power-domain-cells = <0>; + }; + + mfg5@MT8192_POWER_DOMAIN_MFG5 { + reg = ; + #power-domain-cells = <0>; + }; + + mfg6@MT8192_POWER_DOMAIN_MFG6 { + reg = ; + #power-domain-cells = <0>; + }; + }; + }; + + disp@MT8192_POWER_DOMAIN_DISP { + reg = ; + clocks = <&topckgen CLK_TOP_DISP_SEL>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "disp", "disp-0", "disp-1", "disp-2", + "disp-3"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + ipe@MT8192_POWER_DOMAIN_IPE { + reg = ; + clocks = <&topckgen CLK_TOP_IPE_SEL>, + <&ipesys CLK_IPE_LARB19>, + <&ipesys CLK_IPE_LARB20>, + <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_GALS>; + clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", + "ipe-3"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + isp@MT8192_POWER_DOMAIN_ISP { + reg = ; + clocks = <&topckgen CLK_TOP_IMG1_SEL>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "isp", "isp-0", "isp-1"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + isp2@MT8192_POWER_DOMAIN_ISP2 { + reg = ; + clocks = <&topckgen CLK_TOP_IMG2_SEL>, + <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_GALS>; + clock-names = "isp2", "isp2-0", "isp2-1"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + mdp@MT8192_POWER_DOMAIN_MDP { + reg = ; + clocks = <&topckgen CLK_TOP_MDP_SEL>, + <&mdpsys CLK_MDP_SMI0>; + clock-names = "mdp", "mdp-0"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + venc@MT8192_POWER_DOMAIN_VENC { + reg = ; + clocks = <&topckgen CLK_TOP_VENC_SEL>, + <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "venc", "venc-0"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + vdec@MT8192_POWER_DOMAIN_VDEC { + reg = ; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + vdec2@MT8192_POWER_DOMAIN_VDEC2 { + reg = ; + clocks = <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names = "vdec2-0", "vdec2-1", + "vdec2-2"; + #power-domain-cells = <0>; + }; + }; + + cam@MT8192_POWER_DOMAIN_CAM { + reg = ; + clocks = <&topckgen CLK_TOP_CAM_SEL>, + <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CCU_GALS>, + <&camsys CLK_CAM_CAM2MM_GALS>; + clock-names = "cam", "cam-0", "cam-1", "cam-2", + "cam-3"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + cam_rawa@MT8192_POWER_DOMAIN_CAM_RAWA { + reg = ; + clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names = "cam_rawa-0"; + #power-domain-cells = <0>; + }; + + cam_rawb@MT8192_POWER_DOMAIN_CAM_RAWB { + reg = ; + clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names = "cam_rawb-0"; + #power-domain-cells = <0>; + }; + + cam_rawc@MT8192_POWER_DOMAIN_CAM_RAWC { + reg = ; + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; + clock-names = "cam_rawc-0"; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8192-wdt"; reg = <0 0x10007000 0 0x100>;