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Sun, 08 Nov 2020 18:03:56 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 8 Nov 2020 18:03:55 -0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 9 Nov 2020 10:03:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 9 Nov 2020 10:03:53 +0800 From: Weiyi Lu To: Matthias Brugger , Rob Herring , Stephen Boyd , Nicolas Boichat Subject: [PATCH v5 13/24] clk: mediatek: Add MT8192 imgsys clock support Date: Mon, 9 Nov 2020 10:03:38 +0800 Message-ID: <1604887429-29445-14-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1604887429-29445-1-git-send-email-weiyi.lu@mediatek.com> References: <1604887429-29445-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201108_210400_953814_2603F86B X-CRM114-Status: GOOD ( 17.82 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Yingjoe Chen , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Add MT8192 imgsys and imgsys2 clock providers Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/Kconfig | 6 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8192-img.c | 70 +++++++++++++++++++++++++++++++++++ 3 files changed, 77 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8192-img.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index a75b7ec..eb549f8 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -509,6 +509,12 @@ config COMMON_CLK_MT8192_CAMSYS help This driver supports MediaTek MT8192 camsys and camsys_raw clocks. +config COMMON_CLK_MT8192_IMGSYS + bool "Clock driver for MediaTek MT8192 imgsys" + depends on COMMON_CLK_MT8192 + help + This driver supports MediaTek MT8192 imgsys and imgsys2 clocks. + config COMMON_CLK_MT8516 bool "Clock driver for MediaTek MT8516" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 94bf7a0..91392cb 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -70,5 +70,6 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o +obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS) += clk-mt8192-img.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8192-img.c b/drivers/clk/mediatek/clk-mt8192-img.c new file mode 100644 index 0000000..24b4143 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8192-img.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (c) 2020 MediaTek Inc. +// Author: Weiyi Lu + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs img_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate img_clks[] = { + GATE_IMG(CLK_IMG_LARB9, "img_larb9", "img1_sel", 0), + GATE_IMG(CLK_IMG_LARB10, "img_larb10", "img1_sel", 1), + GATE_IMG(CLK_IMG_DIP, "img_dip", "img1_sel", 2), + GATE_IMG(CLK_IMG_GALS, "img_gals", "img1_sel", 12), +}; + +static const struct mtk_gate img2_clks[] = { + GATE_IMG(CLK_IMG2_LARB11, "img2_larb11", "img1_sel", 0), + GATE_IMG(CLK_IMG2_LARB12, "img2_larb12", "img1_sel", 1), + GATE_IMG(CLK_IMG2_MFB, "img2_mfb", "img1_sel", 6), + GATE_IMG(CLK_IMG2_WPE, "img2_wpe", "img1_sel", 7), + GATE_IMG(CLK_IMG2_MSS, "img2_mss", "img1_sel", 8), + GATE_IMG(CLK_IMG2_GALS, "img2_gals", "img1_sel", 12), +}; + +static const struct mtk_clk_desc img_desc = { + .clks = img_clks, + .num_clks = ARRAY_SIZE(img_clks), +}; + +static const struct mtk_clk_desc img2_desc = { + .clks = img2_clks, + .num_clks = ARRAY_SIZE(img2_clks), +}; + +static const struct of_device_id of_match_clk_mt8192_img[] = { + { + .compatible = "mediatek,mt8192-imgsys", + .data = &img_desc, + }, { + .compatible = "mediatek,mt8192-imgsys2", + .data = &img2_desc, + }, { + /* sentinel */ + } +}; + +static struct platform_driver clk_mt8192_img_drv = { + .probe = mtk_clk_simple_probe, + .driver = { + .name = "clk-mt8192-img", + .of_match_table = of_match_clk_mt8192_img, + }, +}; + +builtin_platform_driver(clk_mt8192_img_drv);