diff mbox series

[v4,2/4] dts: arm64: mt8183: Add Mediatek MDP3 nodes

Message ID 1605839346-10648-3-git-send-email-daoyuan.huang@mediatek.com (mailing list archive)
State New
Headers show
Series media: mediatek: support mdp3 on mt8183 platform | expand

Commit Message

Daoyuan Huang Nov. 20, 2020, 2:29 a.m. UTC
From: daoyuan huang <daoyuan.huang@mediatek.com>

Add device nodes for Media Data Path 3 (MDP3) modules.

Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
---
Depend on:
   [1] https://lore.kernel.org/patchwork/patch/1164746/
   [2] https://patchwork.kernel.org/patch/11703299/
   [3] https://patchwork.kernel.org/patch/11283773/
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 116 +++++++++++++++++++++++
 1 file changed, 116 insertions(+)

Comments

Fabien Parent Nov. 20, 2020, 3:15 p.m. UTC | #1
Hi Daoyuan,

> Depend on:
>    [1] https://lore.kernel.org/patchwork/patch/1164746/
>    [2] https://patchwork.kernel.org/patch/11703299/
>    [3] https://patchwork.kernel.org/patch/11283773/

Can you provide an updated list of dependencies because it seems this
patch depends on more than the patch aboves. I applied the related
patch series above but there is still missing node
ERROR (phandle_references): /soc/mdp-rdma0@14001000: Reference to
non-existent node or label "scp"
ERROR (phandle_references): /soc/mdp-rdma0@14001000: Reference to
non-existent node or label "mutex"

It would be even better if you could provide a branch with all the
dependencies included.

>                 mmsys: syscon@14000000 {
>                         compatible = "mediatek,mt8183-mmsys", "syscon";
> +                       mdp-comps = "mediatek,mt8183-mdp-dl",
> +                                   "mediatek,mt8183-mdp-dl";
> +                       mdp-comp-ids = <0 1>;
>                         reg = <0 0x14000000 0 0x1000>;
> +                       mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>                         #clock-cells = <1>;
> +                       clocks = <&mmsys CLK_MM_MDP_DL_TXCK>,
> +                                <&mmsys CLK_MM_MDP_DL_RX>,
> +                                <&mmsys CLK_MM_IPU_DL_TXCK>,
> +                                <&mmsys CLK_MM_IPU_DL_RX>;
> +               };

The kernel is not booting anymore when the 4 clocks above are added,
if I remove them I can boot again. See the following log:

[    0.401314] Unable to handle kernel paging request at virtual
address fffffffffffffffe
[    0.402320] Mem abort info:
[    0.402674]   ESR = 0x96000004
[    0.403062]   EC = 0x25: DABT (current EL), IL = 32 bits
[    0.403741]   SET = 0, FnV = 0
[    0.404128]   EA = 0, S1PTW = 0
[    0.404526] Data abort info:
[    0.404890]   ISV = 0, ISS = 0x00000004
[    0.405374]   CM = 0, WnR = 0
[    0.405751] swapper pgtable: 4k pages, 48-bit VAs, pgdp=00000000415ee000
[    0.406595] [fffffffffffffffe] pgd=0000000000000000, p4d=0000000000000000
[    0.407457] Internal error: Oops: 96000004 [#1] PREEMPT SMP
[    0.408160] Modules linked in:
[    0.408551] CPU: 4 PID: 51 Comm: kworker/4:1 Not tainted
5.9.0-mtk-00010-g121ba830623e-dirty #2
[    0.409646] Hardware name: MediaTek MT8183 evaluation board (DT)
[    0.410416] Workqueue: events deferred_probe_work_func
[    0.411067] pstate: 20000005 (nzCv daif -PAN -UAO BTYPE=--)
[    0.411772] pc : clk_prepare+0x18/0x44
[    0.412252] lr : scpsys_power_on+0x1e8/0x470
[    0.412791] sp : ffff800011fa3a20
[    0.413209] x29: ffff800011fa3a20 x28: 0000000000000000
[    0.413881] x27: 0000000000000000 x26: 0000000000000000
[    0.414551] x25: ffff00007a23ade0 x24: ffff00007a223b80
[    0.415222] x23: ffff800011f5d30c x22: ffff00007a23a888
[    0.415892] x21: fffffffffffffffe x20: 0000000000000000
[    0.416563] x19: 0000000000000000 x18: 0000000000000020
[    0.417233] x17: 0000000000000020 x16: 0000000052d9c4c7
[    0.417904] x15: 0000000000000059 x14: ffff00007a23a640
[    0.418575] x13: ffff00007a23a5c0 x12: 0000000000000000
[    0.419245] x11: ffff8000108331c0 x10: ffff800010833030
[    0.419916] x9 : 0000000000000000 x8 : ffff00007a751c00
[    0.420587] x7 : ffff800011fa3a70 x6 : 00000000130f968d
[    0.421257] x5 : ffff8000110043f0 x4 : 0000000000000184
[    0.421927] x3 : 0000000000000000 x2 : 0000000000000008
[    0.422598] x1 : 000000000000000d x0 : fffffffffffffffe
[    0.423268] Call trace:
[    0.423581]  clk_prepare+0x18/0x44
[    0.424014]  scpsys_power_on+0x1e8/0x470
[    0.424511]  scpsys_probe+0x3f4/0x66c
[    0.424975]  platform_drv_probe+0x54/0xb0
[    0.425483]  really_probe+0xe4/0x490
[    0.425937]  driver_probe_device+0x58/0xc0
[    0.426456]  __device_attach_driver+0xa8/0x10c
[    0.427019]  bus_for_each_drv+0x78/0xcc
[    0.427504]  __device_attach+0xdc/0x180
[    0.427990]  device_initial_probe+0x14/0x20
[    0.428521]  bus_probe_device+0x9c/0xa4
[    0.429007]  deferred_probe_work_func+0x74/0xb0
[    0.429582]  process_one_work+0x1cc/0x350
[    0.430090]  worker_thread+0x2c0/0x470
[    0.430565]  kthread+0x154/0x160
[    0.430976]  ret_from_fork+0x10/0x30
[    0.431431] Code: 910003fd f9000bf3 52800013 b40000e0 (f9400013)
[    0.432200] ---[ end trace d3ecf925b254a559 ]---
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 8fed72bb35d7..fdd809883ce7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -6,6 +6,7 @@ 
  */
 
 #include <dt-bindings/clock/mt8183-clk.h>
+#include <dt-bindings/gce/mt8183-gce.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/reset-controller/mt8183-resets.h>
@@ -712,13 +713,128 @@ 
 
 		mmsys: syscon@14000000 {
 			compatible = "mediatek,mt8183-mmsys", "syscon";
+			mdp-comps = "mediatek,mt8183-mdp-dl",
+				    "mediatek,mt8183-mdp-dl";
+			mdp-comp-ids = <0 1>;
 			reg = <0 0x14000000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 			#clock-cells = <1>;
+			clocks = <&mmsys CLK_MM_MDP_DL_TXCK>,
+				 <&mmsys CLK_MM_MDP_DL_RX>,
+				 <&mmsys CLK_MM_IPU_DL_TXCK>,
+				 <&mmsys CLK_MM_IPU_DL_RX>;
+		};
+
+		mdp_rdma0: mdp-rdma0@14001000 {
+			compatible = "mediatek,mt8183-mdp-rdma",
+				     "mediatek,mt8183-mdp3";
+			mediatek,scp = <&scp>;
+			mediatek,mdp-id = <0>;
+			reg = <0 0x14001000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
+			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+				 <&mmsys CLK_MM_MDP_RSZ1>;
+			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+			mediatek,larb = <&larb0>;
+			mediatek,mmsys = <&mmsys>;
+			mediatek,mm-mutex = <&mutex>;
+			mediatek,imgsys = <&imgsys>;
+			mediatek,mailbox-gce = <&gce>;
+			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+				 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
+				 <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
+				 <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
+			gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
+				     <&gce 0x14010000 SUBSYS_1401XXXX>,
+				     <&gce 0x14020000 SUBSYS_1402XXXX>,
+				     <&gce 0x15020000 SUBSYS_1502XXXX>;
+			mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
+					      <CMDQ_EVENT_MDP_RDMA0_EOF>,
+					      <CMDQ_EVENT_MDP_RSZ0_SOF>,
+					      <CMDQ_EVENT_MDP_RSZ1_SOF>,
+					      <CMDQ_EVENT_MDP_TDSHP_SOF>,
+					      <CMDQ_EVENT_MDP_WROT0_SOF>,
+					      <CMDQ_EVENT_MDP_WROT0_EOF>,
+					      <CMDQ_EVENT_MDP_WDMA0_SOF>,
+					      <CMDQ_EVENT_MDP_WDMA0_EOF>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
+					      <CMDQ_EVENT_WPE_A_DONE>,
+					      <CMDQ_EVENT_SPE_B_DONE>;
+		};
+
+		mdp_rsz0: mdp-rsz0@14003000 {
+			compatible = "mediatek,mt8183-mdp-rsz";
+			mediatek,mdp-id = <0>;
+			reg = <0 0x14003000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+		};
+
+		mdp_rsz1: mdp-rsz1@14004000 {
+			compatible = "mediatek,mt8183-mdp-rsz";
+			mediatek,mdp-id = <1>;
+			reg = <0 0x14004000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+		};
+
+		mdp_wrot0: mdp-wrot0@14005000 {
+			compatible = "mediatek,mt8183-mdp-wrot";
+			mediatek,mdp-id = <0>;
+			mdp-comps = "mediatek,mt8183-mdp-path";
+			mdp-comp-ids = <0>;
+			reg = <0 0x14005000 0 0x1000>;
+			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_WROT0>;
+			iommus = <&iommu M4U_PORT_MDP_WROT0>;
+			mediatek,larb = <&larb0>;
+		};
+
+		mdp_wdma: mdp-wdma@14006000 {
+			compatible = "mediatek,mt8183-mdp-wdma";
+			mediatek,mdp-id = <0>;
+			mdp-comps = "mediatek,mt8183-mdp-path";
+			mdp-comp-ids = <1>;
+			reg = <0 0x14006000 0 0x1000>;
+			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+			iommus = <&iommu M4U_PORT_MDP_WDMA0>;
+			mediatek,larb = <&larb0>;
+		};
+
+		mdp_ccorr: mdp-ccorr@1401c000 {
+			compatible = "mediatek,mt8183-mdp-ccorr";
+			mediatek,mdp-id = <0>;
+			reg = <0 0x1401c000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_CCORR>;
 		};
 
 		imgsys: syscon@15020000 {
 			compatible = "mediatek,mt8183-imgsys", "syscon";
+			mediatek,mdp-id = <0>;
+			mdp-comps = "mediatek,mt8183-mdp-imgi",
+				    "mediatek,mt8183-mdp-exto";
+			mdp-comp-ids = <0 1>;
 			reg = <0 0x15020000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1502XXXX 0 0x1000>;
 			#clock-cells = <1>;
 		};