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Fri, 11 Dec 2020 20:12:08 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Dec 2020 20:12:06 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 12 Dec 2020 12:12:06 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 12 Dec 2020 12:12:05 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , "Rob Herring" , Matthias Brugger Subject: [PATCH v2, 07/17] drm/mediatek: add disp config and mm 26mhz clock into mutex device Date: Sat, 12 Dec 2020 12:11:47 +0800 Message-ID: <1607746317-4696-8-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1607746317-4696-1-git-send-email-yongqiang.niu@mediatek.com> References: <1607746317-4696-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201211_231211_624362_F1A4C51A X-CRM114-Status: GOOD ( 18.27 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Yongqiang Niu , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Daniel Vetter , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org there are 2 more clock need enable for display. parser these clock when mutex device probe, enable and disable when mutex on/off Signed-off-by: Yongqiang Niu --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 49 ++++++++++++++++++++++++++++------ 1 file changed, 41 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 60788c1..de618a1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -118,7 +118,7 @@ struct mtk_ddp_data { struct mtk_ddp { struct device *dev; - struct clk *clk; + struct clk *clk[3]; void __iomem *regs; struct mtk_disp_mutex mutex[10]; const struct mtk_ddp_data *data; @@ -257,14 +257,39 @@ int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); - return clk_prepare_enable(ddp->clk); + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) { + if (IS_ERR(ddp->clk[i])) + continue; + ret = clk_prepare_enable(ddp->clk[i]); + if (ret) { + pr_err("failed to enable clock, err %d. i:%d\n", + ret, i); + goto err; + } + } + + return 0; + +err: + while (--i >= 0) + clk_disable_unprepare(ddp->clk[i]); + return ret; } void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); - clk_disable_unprepare(ddp->clk); + int i; + + for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) { + if (IS_ERR(ddp->clk[i])) + continue; + clk_disable_unprepare(ddp->clk[i]); + } } void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, @@ -415,11 +440,19 @@ static int mtk_ddp_probe(struct platform_device *pdev) ddp->data = of_device_get_match_data(dev); if (!ddp->data->no_clk) { - ddp->clk = devm_clk_get(dev, NULL); - if (IS_ERR(ddp->clk)) { - if (PTR_ERR(ddp->clk) != -EPROBE_DEFER) - dev_err(dev, "Failed to get clock\n"); - return PTR_ERR(ddp->clk); + int ret; + + for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) { + ddp->clk[i] = of_clk_get(dev->of_node, i); + + if (IS_ERR(ddp->clk[i])) { + ret = PTR_ERR(ddp->clk[i]); + if (ret != EPROBE_DEFER) + dev_err(dev, "Failed to get clock %d\n", + ret); + + return ret; + } } }