diff mbox series

arm64: dts: mediatek: Add Mediatek mt8192 cpufreq device nodes

Message ID 1608521814-13017-1-git-send-email-andrew-sh.cheng@mediatek.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: mediatek: Add Mediatek mt8192 cpufreq device nodes | expand

Commit Message

andrew-sh.cheng Dec. 21, 2020, 3:36 a.m. UTC 
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>

This patch depends on [1] and [2].

[1]http://lists.infradead.org/pipermail/linux-mediatek/2020-November/019378.html
[2]https://patchwork.kernel.org/project/linux-mediatek/patch/1607586516-6547-3-git-send-email-hector.yuan@mediatek.com/

Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 69d45c7b31f1..770f7d8833db 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -39,6 +39,7 @@ 
 			compatible = "arm,cortex-a55";
 			reg = <0x000>;
 			enable-method = "psci";
+			performance-domain = <&performance 0>;
 			clock-frequency = <1701000000>;
 			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <530>;
@@ -49,6 +50,7 @@ 
 			compatible = "arm,cortex-a55";
 			reg = <0x100>;
 			enable-method = "psci";
+			performance-domain = <&performance 0>;
 			clock-frequency = <1701000000>;
 			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <530>;
@@ -59,6 +61,7 @@ 
 			compatible = "arm,cortex-a55";
 			reg = <0x200>;
 			enable-method = "psci";
+			performance-domain = <&performance 0>;
 			clock-frequency = <1701000000>;
 			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <530>;
@@ -69,6 +72,7 @@ 
 			compatible = "arm,cortex-a55";
 			reg = <0x300>;
 			enable-method = "psci";
+			performance-domain = <&performance 0>;
 			clock-frequency = <1701000000>;
 			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <530>;
@@ -79,6 +83,7 @@ 
 			compatible = "arm,cortex-a76";
 			reg = <0x400>;
 			enable-method = "psci";
+			performance-domain = <&performance 1>;
 			clock-frequency = <2171000000>;
 			next-level-cache = <&l2_1>;
 			capacity-dmips-mhz = <1024>;
@@ -89,6 +94,7 @@ 
 			compatible = "arm,cortex-a76";
 			reg = <0x500>;
 			enable-method = "psci";
+			performance-domain = <&performance 1>;
 			clock-frequency = <2171000000>;
 			next-level-cache = <&l2_1>;
 			capacity-dmips-mhz = <1024>;
@@ -99,6 +105,7 @@ 
 			compatible = "arm,cortex-a76";
 			reg = <0x600>;
 			enable-method = "psci";
+			performance-domain = <&performance 1>;
 			clock-frequency = <2171000000>;
 			next-level-cache = <&l2_1>;
 			capacity-dmips-mhz = <1024>;
@@ -109,6 +116,7 @@ 
 			compatible = "arm,cortex-a76";
 			reg = <0x700>;
 			enable-method = "psci";
+			performance-domain = <&performance 1>;
 			clock-frequency = <2171000000>;
 			next-level-cache = <&l2_1>;
 			capacity-dmips-mhz = <1024>;
@@ -194,6 +202,12 @@ 
 		compatible = "simple-bus";
 		ranges;
 
+		performance: performance-controller@0011bc00 {
+			compatible = "mediatek,cpufreq-hw";
+			reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+			#performance-domain-cells = <1>;
+		};
+
 		gic: interrupt-controller@c000000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <4>;