From patchwork Thu Mar 18 05:40:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12147367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB8A2C433DB for ; Thu, 18 Mar 2021 05:42:15 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 586A064F06 for ; Thu, 18 Mar 2021 05:42:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 586A064F06 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=QpoAR8Ftv461jv6PnBWW8Cv7Q5D8KwZ8AbEZ5dPTIT0=; b=k9qKxFMHKL2rqM8apfyZowpb1 A0FcF1nBgSER0JvgybjmPi3DbQbaVlF3Uv7lBbdF9LXikIjRZDFibBEoT6EneieR3RrMEjq+7uUgf /2qURmVAZtaGYruPPwVuIG7dG6ebS3F72hUmkzwukpfN0uINW+Nb9ZSVopQbDnMqyD4L3bOwNj9I8 iXWvHhsuBlYJz1zO1HT/SxmnRsK8bRAVX7Tx+xApIzAu4icNQkxU+WXtR8purslVg5+AW5xO3oG8c UZfEyyUckl0XeG7rzhMHfx3re9oY2isrGH/kchOIbqwUjGHM6i+VA0RHCyRPg8c+eb0PWAbnrt1K3 EdAPcS2Pw==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lMlQ0-004XXg-GU; Thu, 18 Mar 2021 05:42:00 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lMlPs-004XWa-T5; Thu, 18 Mar 2021 05:41:55 +0000 X-UUID: 4f877bb5b7b04d7dba84ceb76d898ef6-20210317 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=y1PytY+UmqOv/UQBVRFvBrqPxBWsx21tYPt9bYVR4Ek=; b=heheD7BEltSXCA58Dvln25zSH4HP8YNzqlwrSf/vWSSAieeQs5vspGoZK9QU4Jh4PgujMLbNMSpEaJUaDvqLdb8qnoWxSSIdeWwdlCYAv8WYEm+oD2nIqkWNDwAqTrXlBOhraPQZXauKNyY8UiXqHf252yWJf4UcI5pyMBFsuPw=; X-UUID: 4f877bb5b7b04d7dba84ceb76d898ef6-20210317 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1803575843; Wed, 17 Mar 2021 21:41:43 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Mar 2021 22:41:41 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Mar 2021 13:41:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Mar 2021 13:41:40 +0800 From: Rex-BC Chen To: , CC: , , , , , Rex-BC Chen , Pi-Hsun Shih , Jitao Shi Subject: [v5, 1/2] drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid Date: Thu, 18 Mar 2021 13:40:55 +0800 Message-ID: <1616046056-29068-2-git-send-email-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1616046056-29068-1-git-send-email-rex-bc.chen@mediatek.com> References: <1616046056-29068-1-git-send-email-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210318_054153_431022_868AC7B9 X-CRM114-Status: GOOD ( 11.64 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid. Signed-off-by: Pi-Hsun Shih Signed-off-by: Rex-BC Chen Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dpi.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index b05f900d9322..0b427ad0cd9b 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit { struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); u32 reg_h_fre_con; + u32 max_clock_khz; bool edge_sel_en; }; @@ -557,9 +558,23 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) mtk_dpi_set_display_mode(dpi, &dpi->mode); } +static enum drm_mode_status +mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct mtk_dpi *dpi = bridge_to_dpi(bridge); + + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { .attach = mtk_dpi_bridge_attach, .mode_set = mtk_dpi_bridge_mode_set, + .mode_valid = mtk_dpi_bridge_mode_valid, .disable = mtk_dpi_bridge_disable, .enable = mtk_dpi_bridge_enable, }; @@ -668,17 +683,20 @@ static unsigned int mt8183_calculate_factor(int clock) static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, + .max_clock_khz = 300000, }; static const struct mtk_dpi_conf mt2701_conf = { .cal_factor = mt2701_calculate_factor, .reg_h_fre_con = 0xb0, .edge_sel_en = true, + .max_clock_khz = 150000, }; static const struct mtk_dpi_conf mt8183_conf = { .cal_factor = mt8183_calculate_factor, .reg_h_fre_con = 0xe0, + .max_clock_khz = 100000, }; static int mtk_dpi_probe(struct platform_device *pdev)