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Tue, 06 Apr 2021 20:36:02 -0700 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 6 Apr 2021 20:28:41 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 7 Apr 2021 11:28:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 7 Apr 2021 11:28:39 +0800 From: Flora Fu To: Rob Herring , Matthias Brugger , Michael Turquette , Stephen Boyd , Liam Girdwood , "Mark Brown" CC: Flora Fu , Pi-Cheng Chen , Chiawen Lee , Chun-Jie Chen , , , , , Subject: [PATCH 2/8] clk: mediatek: mt8192: Add APU clocks support Date: Wed, 7 Apr 2021 11:28:00 +0800 Message-ID: <1617766086-5502-3-git-send-email-flora.fu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1617766086-5502-1-git-send-email-flora.fu@mediatek.com> References: <1617766086-5502-1-git-send-email-flora.fu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 898ED09CD3F7ED923A39CBC5AC5322F6610F0DE99905E8BF78FE993B60231D142000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210407_043615_241284_E440EDB6 X-CRM114-Status: GOOD ( 10.35 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add APU clocks support on MT8192. Signed-off-by: Flora Fu --- drivers/clk/mediatek/clk-mt8192.c | 91 +++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index bf6a2084a348..4eb61f006306 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -244,6 +244,65 @@ static const char * const ccu_parents[] = { "univpll_d6_d2" }; +static const char * const dsp_parents[] = { + "clk26m", + "univpll_d6_d2", + "univpll_d4_d2", + "univpll_d5", + "univpll_d4", + "mmpll_d4", + "mainpll_d3", + "univpll_d3" +}; + +static const char * const dsp1_parents[] = { + "clk26m", + "npupll_ck", + "mainpll_d4_d2", + "univpll_d5", + "univpll_d4", + "mainpll_d3", + "univpll_d3", + "apupll_ck" +}; + +static const char * const dsp1_npupll_parents[] = { + "dsp1_sel", + "npupll_ck" +}; + +static const char * const dsp2_parents[] = { + "clk26m", + "npupll_ck", + "mainpll_d4_d2", + "univpll_d5", + "univpll_d4", + "mainpll_d3", + "univpll_d3", + "apupll_ck" +}; + +static const char * const dsp2_npupll_parents[] = { + "dsp2_sel", + "npupll_ck" +}; + +static const char * const dsp5_parents[] = { + "clk26m", + "apupll_ck", + "univpll_d4_d2", + "mainpll_d4", + "univpll_d4", + "mmpll_d4", + "mainpll_d3", + "univpll_d3" +}; + +static const char * const dsp5_apupll_parents[] = { + "dsp5_sel", + "apupll_ck" +}; + static const char * const dsp7_parents[] = { "clk26m", "mainpll_d4_d2", @@ -255,6 +314,17 @@ static const char * const dsp7_parents[] = { "mmpll_d4" }; +static const char * const ipu_if_parents[] = { + "clk26m", + "univpll_d6_d2", + "mainpll_d4_d2", + "univpll_d4_d2", + "univpll_d5", + "mainpll_d4", + "tvdpll_ck", + "univpll_d4" +}; + static const char * const mfg_ref_parents[] = { "clk26m", "clk26m", @@ -734,9 +804,26 @@ static const struct mtk_mux top_mtk_muxes[] = { cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10), MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel", ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11), + /* CLK_CFG_3 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", + dsp_parents, 0x040, 0x044, 0x048, 0, 3, 7, 0x004, 12), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1_SEL, "dsp1_sel", + dsp1_parents, 0x040, 0x044, 0x048, 8, 3, 15, 0x004, 13), + MUX_CLR_SET_UPD(CLK_TOP_DSP1_NPUPLL_SEL, "dsp1_npupll_sel", + dsp1_npupll_parents, 0x040, 0x044, 0x048, 11, 1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2_SEL, "dsp2_sel", + dsp2_parents, 0x040, 0x044, 0x048, 16, 3, 23, 0x004, 14), + MUX_CLR_SET_UPD(CLK_TOP_DSP2_NPUPLL_SEL, "dsp2_npupll_sel", + dsp2_npupll_parents, 0x040, 0x044, 0x048, 19, 1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5_SEL, "dsp5_sel", + dsp5_parents, 0x040, 0x044, 0x048, 24, 3, 31, 0x004, 15), + MUX_CLR_SET_UPD(CLK_TOP_DSP5_APUPLL_SEL, "dsp5_apupll_sel", + dsp5_apupll_parents, 0x040, 0x044, 0x048, 27, 1, -1, -1), /* CLK_CFG_4 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel", dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16), + MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF_SEL, "ipu_if_sel", + ipu_if_parents, 0x050, 0x054, 0x058, 8, 3, 15, 0x004, 17), MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel", mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18), MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", @@ -1175,6 +1262,10 @@ static const struct mtk_pll_data plls[] = { 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0), PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000, 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), + PLL_B(CLK_APMIXED_APUPLL, "apupll", 0x03a0, 0x03ac, 0xff000001, + HAVE_RST_BAR, BIT(23), 22, 0x03a4, 24, 0, 0, 0, 0x03a4, 0), + PLL_B(CLK_APMIXED_NPUPLL, "npupll", 0x03b4, 0x03c0, 0x00000001, + 0, 0, 22, 0x03b8, 24, 0, 0, 0, 0x03b8, 0), }; static struct clk_onecell_data *top_clk_data;