From patchwork Thu Jan 26 16:21:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Kurtz X-Patchwork-Id: 9539735 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6B2C5604A0 for ; Thu, 26 Jan 2017 16:25:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5BB8E204C1 for ; Thu, 26 Jan 2017 16:25:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 505C227F9F; Thu, 26 Jan 2017 16:25:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_SORBS_SPAM,T_DKIM_INVALID autolearn=no version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 68B8B204C1 for ; Thu, 26 Jan 2017 16:25:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cWmrb-0000En-0t; Thu, 26 Jan 2017 16:25:31 +0000 Received: from mail-pf0-f172.google.com ([209.85.192.172]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cWmpg-0005ym-CT for linux-mediatek@lists.infradead.org; Thu, 26 Jan 2017 16:23:34 +0000 Received: by mail-pf0-f172.google.com with SMTP id y143so66378862pfb.0 for ; Thu, 26 Jan 2017 08:23:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NFe8oHpuU/3I37yN0U8ihUofwz6qNN90DseixYXrsPE=; b=RPgwQGT7ebLQucpCGOXUKL8kkXwvI9d3h3rZ+zxbzoE3E1wSlqHpAavlJ1ZKrZyYgc D+iVZCl0OMWuyaTHRSIiSTm3ivB39jkkUvGvxuf/UskW+pSzn+4iaJU2O2avDxd/fSAi 5WHM632hxGycwhbFT8m6azhHa2ECq96xkIGFA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NFe8oHpuU/3I37yN0U8ihUofwz6qNN90DseixYXrsPE=; b=rTbEWC/g3KrqypaQQb7he72tPAgRAe5SKJpysdNn3UK86Vz6me74A7uSeukbswqFHr yha7moF3TUzW2WHx30pEFrTNlzmy3DNffrqk7qjVDoZvKtY6Qw7uxFgsBXoINH76GSo+ NfMtygkeUwl0YN5uUAd4tUIfbkF+Ryzsex2IW71Cmd8e75nHWbAweHA4u6XGqSOSmsFs UqKdhfhCkw5eVAzWPYQd21/DvfPQXya6t8yEvO11pvtTuZBNsAoiGHuu6db3HJbkVB00 00UiI0BLDDo6NA9wDtXLyjkGScOPBeUEgU5KfuokGZR+ViDe5apQ3CFBRmxs/Xvl5O+K iclQ== X-Gm-Message-State: AIkVDXLxFKQF/nMJsQZUPAP3ERh8etDqoRQDfHnrts2iKclt3618yvnJkcCk14BvjKNmgfYp X-Received: by 10.98.92.4 with SMTP id q4mr3905165pfb.151.1485447731528; Thu, 26 Jan 2017 08:22:11 -0800 (PST) Received: from djkurtz-z840.tpe.corp.google.com ([172.30.210.11]) by smtp.gmail.com with ESMTPSA id z77sm4607751pfk.47.2017.01.26.08.22.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Jan 2017 08:22:11 -0800 (PST) From: Daniel Kurtz To: Subject: [PATCH 2/2] spi: mediatek: Only do dma for 4-byte aligned buffers Date: Fri, 27 Jan 2017 00:21:54 +0800 Message-Id: <20170126162154.124287-2-djkurtz@chromium.org> X-Mailer: git-send-email 2.11.0.483.g087da7b7c-goog In-Reply-To: <20170126162154.124287-1-djkurtz@chromium.org> References: <20170126162154.124287-1-djkurtz@chromium.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170126_082332_556623_2CBD2914 X-CRM114-Status: GOOD ( 14.99 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drinkcat@chromium.org, Leilk Liu , dtor@chromium.org, open list , "open list:SPI SUBSYSTEM" , Matthias Brugger , Mark Brown , "moderated list:ARM/Mediatek SoC support" , groeck@chromium.org, Robin Murphy , "moderated list:ARM/Mediatek SoC support" MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Mediatek SPI DMA only works when tx and rx buffer addresses are 4-byte aligned. Unaligned DMA transactions appeared to work previously, since we the spi core was incorrectly using the spi_master device for dma, which had a 0 dma_mask, and therefore the swiotlb dma map operations were falling back to using bounce buffers. Since each DMA transaction would use its own buffer, the mapped starting address of each transaction was always aligned. When doing real DMA, the mapped address will share the alignment of the raw tx/rx buffer provided by the SPI user, which may or may not be aligned. If a buffer is not aligned, we cannot use DMA, and must use FIFO based transaction instead. So, this patch implements a scheme that allows using the FIFO for arbitrary length transactions (larger than the 32-byte FIFO size) by reloading the FIFO in the interrupt handler. Signed-off-by: Daniel Kurtz Cc: Leilk Liu --- drivers/spi/spi-mt65xx.c | 37 +++++++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 899d7a8f0889..4b592fc25194 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -73,7 +73,7 @@ #define MTK_SPI_IDLE 0 #define MTK_SPI_PAUSED 1 -#define MTK_SPI_MAX_FIFO_SIZE 32 +#define MTK_SPI_MAX_FIFO_SIZE 32U #define MTK_SPI_PACKET_SIZE 1024 struct mtk_spi_compatible { @@ -333,7 +333,7 @@ static int mtk_spi_fifo_transfer(struct spi_master *master, struct mtk_spi *mdata = spi_master_get_devdata(master); mdata->cur_transfer = xfer; - mdata->xfer_len = xfer->len; + mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); mtk_spi_prepare_transfer(master, xfer); mtk_spi_setup_packet(master); @@ -410,7 +410,10 @@ static bool mtk_spi_can_dma(struct spi_master *master, struct spi_device *spi, struct spi_transfer *xfer) { - return xfer->len > MTK_SPI_MAX_FIFO_SIZE; + /* Buffers for DMA transactions must be 4-byte aligned */ + return (xfer->len > MTK_SPI_MAX_FIFO_SIZE && + (unsigned long)xfer->tx_buf % 4 == 0 && + (unsigned long)xfer->rx_buf % 4 == 0); } static int mtk_spi_setup(struct spi_device *spi) @@ -451,7 +454,33 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) ®_val, remainder); } } - spi_finalize_current_transfer(master); + + trans->len -= mdata->xfer_len; + if (!trans->len) { + spi_finalize_current_transfer(master); + return IRQ_HANDLED; + } + + if (trans->tx_buf) + trans->tx_buf += mdata->xfer_len; + if (trans->rx_buf) + trans->rx_buf += mdata->xfer_len; + + mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, trans->len); + mtk_spi_setup_packet(master); + + cnt = trans->len / 4; + iowrite32_rep(mdata->base + SPI_TX_DATA_REG, trans->tx_buf, cnt); + + remainder = trans->len % 4; + if (remainder > 0) { + reg_val = 0; + memcpy(®_val, trans->tx_buf + (cnt * 4), remainder); + writel(reg_val, mdata->base + SPI_TX_DATA_REG); + } + + mtk_spi_enable_transfer(master); + return IRQ_HANDLED; }