| Message ID | 20190220025357.7354-6-wangyan.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | make mt7623 clock of hdmi stable | expand |
Quoting wangyan wang (2019-02-19 18:53:54) > From: chunhui dai <chunhui.dai@mediatek.com> > > Add MUX_GATE_FLAGS_2 for the clock which needs to set two falgs. s/falgs/flags/ > Such as some mux need to set the flags of "CLK_MUX_ROUND_CLOSEST". > > Signed-off-by: chunhui dai <chunhui.dai@mediatek.com> > Signed-off-by: wangyan wang <wangyan.wang@mediatek.com> > --- > drivers/clk/mediatek/clk-mtk.c | 2 +- > drivers/clk/mediatek/clk-mtk.h | 20 ++++++++++++++------ > 2 files changed, 15 insertions(+), 7 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c > index 9c0ae4278a94..2ed996404804 100644 > --- a/drivers/clk/mediatek/clk-mtk.c > +++ b/drivers/clk/mediatek/clk-mtk.c > @@ -167,7 +167,7 @@ struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, > mux->mask = BIT(mc->mux_width) - 1; > mux->shift = mc->mux_shift; > mux->lock = lock; > - > + mux->flags = mc->mux_flags; > mux_hw = &mux->hw; > mux_ops = &clk_mux_ops; > > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h > index f83c2bbb677e..4b88d196d52f 100644 > --- a/drivers/clk/mediatek/clk-mtk.h > +++ b/drivers/clk/mediatek/clk-mtk.h > @@ -81,15 +81,13 @@ struct mtk_composite { > signed char divider_shift; > signed char divider_width; > > + unsigned char mux_flags; Why isn't it an unsigned long? Isn't this supposed to match the frameworks version of the clk flags?
Dear Stephen, > + unsigned char mux_flags; > > Why isn't it an unsigned long? Isn't this supposed to match the > frameworks version of the clk flags? ----> it is unsigned char mux_flags ,becasuse struct clk_mux { .... .... u8 flags; .... } it is matched when use " mux->flags = mc->mux_flags;" Best Regards Wangyan On Wed, 2019-02-20 at 11:37 -0800, Stephen Boyd wrote: > Quoting wangyan wang (2019-02-19 18:53:54) > > From: chunhui dai <chunhui.dai@mediatek.com> > > > > Add MUX_GATE_FLAGS_2 for the clock which needs to set two falgs. > > s/falgs/flags/ > > > Such as some mux need to set the flags of "CLK_MUX_ROUND_CLOSEST". > > > > Signed-off-by: chunhui dai <chunhui.dai@mediatek.com> > > Signed-off-by: wangyan wang <wangyan.wang@mediatek.com> > > --- > > drivers/clk/mediatek/clk-mtk.c | 2 +- > > drivers/clk/mediatek/clk-mtk.h | 20 ++++++++++++++------ > > 2 files changed, 15 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c > > index 9c0ae4278a94..2ed996404804 100644 > > --- a/drivers/clk/mediatek/clk-mtk.c > > +++ b/drivers/clk/mediatek/clk-mtk.c > > @@ -167,7 +167,7 @@ struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, > > mux->mask = BIT(mc->mux_width) - 1; > > mux->shift = mc->mux_shift; > > mux->lock = lock; > > - > > + mux->flags = mc->mux_flags; > > mux_hw = &mux->hw; > > mux_ops = &clk_mux_ops; > > > > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h > > index f83c2bbb677e..4b88d196d52f 100644 > > --- a/drivers/clk/mediatek/clk-mtk.h > > +++ b/drivers/clk/mediatek/clk-mtk.h > > @@ -81,15 +81,13 @@ struct mtk_composite { > > signed char divider_shift; > > signed char divider_width; > > > > + unsigned char mux_flags; > > Why isn't it an unsigned long? Isn't this supposed to match the > frameworks version of the clk flags? > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
Quoting mtk14994 (2019-02-20 18:34:11) > Dear Stephen, > > + unsigned char mux_flags; > > > > Why isn't it an unsigned long? Isn't this supposed to match the > > frameworks version of the clk flags? > > ----> it is unsigned char mux_flags ,becasuse struct clk_mux { > > .... > .... > u8 flags; > .... > } > > it is matched when use " mux->flags = mc->mux_flags;" > Please try to not top-post. Ok I thought it was the generic clk flags, not the mux specific flag bits. Sounds fine then, but I would sort of expect it to match the type in clk_mux then, i.e. be a u8 instead of an unsigned char (yes it's the same in the end but it looks different at a glance).
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 9c0ae4278a94..2ed996404804 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -167,7 +167,7 @@ struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, mux->mask = BIT(mc->mux_width) - 1; mux->shift = mc->mux_shift; mux->lock = lock; - + mux->flags = mc->mux_flags; mux_hw = &mux->hw; mux_ops = &clk_mux_ops; diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f83c2bbb677e..4b88d196d52f 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -81,15 +81,13 @@ struct mtk_composite { signed char divider_shift; signed char divider_width; + unsigned char mux_flags; + signed char num_parents; }; -/* - * In case the rate change propagation to parent clocks is undesirable, - * this macro allows to specify the clock flags manually. - */ -#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ - _gate, _flags) { \ +#define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ + _width, _gate, _flags, _muxflags) { \ .id = _id, \ .name = _name, \ .mux_reg = _reg, \ @@ -101,8 +99,18 @@ struct mtk_composite { .parent_names = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ .flags = _flags, \ + .mux_flags = _muxflags, \ } +/* + * In case the rate change propagation to parent clocks is undesirable, + * this macro allows to specify the clock flags manually. + */ +#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ + _gate, _flags) \ + MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \ + _shift, _width, _gate, _flags, 0) + /* * Unless necessary, all MUX_GATE clocks propagate rate changes to their * parent clock by default.