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Tue, 10 Sep 2019 03:22:59 +0800 From: To: , , , , Subject: [RFC PATCH V3 1/5] dt-bindings: mt8183: Added DIP dt-bindings Date: Tue, 10 Sep 2019 03:22:40 +0800 Message-ID: <20190909192244.9367-2-frederic.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190909192244.9367-1-frederic.chen@mediatek.com> References: <20190909192244.9367-1-frederic.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190909_122313_106474_82E2AD7E X-CRM114-Status: GOOD ( 10.15 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [216.200.240.184 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shik@chromium.org, devicetree@vger.kernel.org, Sean.Cheng@mediatek.com, Rynn.Wu@mediatek.com, Allan.Yang@mediatek.com, srv_heupstream@mediatek.com, holmes.chiou@mediatek.com, suleiman@chromium.org, Jerry-ch.Chen@mediatek.com, jungo.lin@mediatek.com, sj.huang@mediatek.com, yuzhao@chromium.org, linux-mediatek@lists.infradead.org, zwisler@chromium.org, christie.yu@mediatek.com, frederic.chen@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: Frederic Chen This patch adds DT binding documentation for the Digital Image Processing (DIP) unit of camera ISP system on Mediatek's SoCs. It depends on the SCP and MDP 3 patch as following: 1. dt-bindings: Add a binding for Mediatek SCP https://patchwork.kernel.org/patch/11027247/ 2. dt-binding: mt8183: Add Mediatek MDP3 dt-bindings https://patchwork.kernel.org/patch/10945603/ Signed-off-by: Frederic Chen --- .../bindings/media/mediatek,mt8183-dip.txt | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8183-dip.txt diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8183-dip.txt b/Documentation/devicetree/bindings/media/mediatek,mt8183-dip.txt new file mode 100644 index 000000000000..3a0435513089 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8183-dip.txt @@ -0,0 +1,40 @@ +* Mediatek Digital Image Processor (DIP) + +Digital Image Processor (DIP) unit in Mediatek ISP system is responsible for +image content adjustment according to the tuning parameters. DIP can process +the image form memory buffer and output the processed image to multiple output +buffers. Furthermore, it can support demosaicing and noise reduction on the +images. + +Required properties: +- compatible: "mediatek,mt8183-dip" +- reg: Physical base address and length of the function block register space +- interrupts: interrupt number to the cpu +- iommus: should point to the respective IOMMU block with master port as + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt + for details. +- mediatek,mdp3: should point to the respective mdp block. DIP hardware + connects to MDP and we can get the processed image with both effect of the + two blocks. +- mediatek,larb: must contain the local arbiters in the current SoCs, see + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt + for details. +- mediatek,scp: should point to the scp node since the we use SCP + coprocessor to control DIP hardware +- clocks: must contain the local arbiters 5 (LARB5) and DIP clock +- clock-names: must contain "larb5" and "dip" + +Example: + dip: dip@15022000 { + compatible = "mediatek,mt8183-dip"; + mediatek,larb = <&larb5>; + mediatek,mdp3 = <&mdp_rdma0>; + mediatek,scp = <&scp>; + iommus = <&iommu M4U_PORT_CAM_IMGI>; + reg = <0 0x15022000 0 0x6000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_LARB5>, + <&imgsys CLK_IMG_DIP>; + clock-names = "larb5", + "dip"; + };