| Message ID | 20200505140231.16600-3-brgl@bgdev.pl (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mediatek: add support for MediaTek Ethernet MAC | expand |
On Tue, May 05, 2020 at 04:02:22PM +0200, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bgolaszewski@baylibre.com> > > This adds yaml DT bindings for the MediaTek Ethernet MAC present on the > mt8* family of SoCs. > > Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> > --- > .../bindings/net/mediatek,eth-mac.yaml | 80 +++++++++++++++++++ > 1 file changed, 80 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml > > diff --git a/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml b/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml > new file mode 100644 > index 000000000000..7682fe9d8109 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml > @@ -0,0 +1,80 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/mediatek,eth-mac.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Ethernet MAC Controller > + > +maintainers: > + - Bartosz Golaszewski <bgolaszewski@baylibre.com> > + > +description: > + This Ethernet MAC is used on the MT8* family of SoCs from MediaTek. > + It's compliant with 802.3 standards and supports half- and full-duplex > + modes with flow-control as well as CRC offloading and VLAN tags. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8516-eth > + - mediatek,mt8518-eth > + - mediatek,mt8175-eth > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + minItems: 3 > + maxItems: 3 > + > + clock-names: > + additionalItems: false > + items: > + - const: core > + - const: reg > + - const: trans > + > + mediatek,pericfg: > + $ref: /schemas/types.yaml#definitions/phandle > + description: > + Phandle to the device containing the PERICFG register range. Perhaps say what it is used for? > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - mediatek,pericfg > + - phy-handle > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/mt8516-clk.h> > + > + ethernet: ethernet@11180000 { > + compatible = "mediatek,mt8516-eth"; > + reg = <0 0x11180000 0 0x1000>; Default addr and size is 1 cell. > + mediatek,pericfg = <&pericfg>; > + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&topckgen CLK_TOP_RG_ETH>, > + <&topckgen CLK_TOP_66M_ETH>, > + <&topckgen CLK_TOP_133M_ETH>; > + clock-names = "core", "reg", "trans"; > + phy-handle = <ð_phy>; > + phy-mode = "rmii"; > + > + mdio { Not documented. > + #address-cells = <1>; > + #size-cells = <0>; > + > + eth_phy: ethernet-phy@0 { > + reg = <0>; > + }; > + }; > + }; > -- > 2.25.0 >
diff --git a/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml b/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml new file mode 100644 index 000000000000..7682fe9d8109 --- /dev/null +++ b/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/mediatek,eth-mac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Ethernet MAC Controller + +maintainers: + - Bartosz Golaszewski <bgolaszewski@baylibre.com> + +description: + This Ethernet MAC is used on the MT8* family of SoCs from MediaTek. + It's compliant with 802.3 standards and supports half- and full-duplex + modes with flow-control as well as CRC offloading and VLAN tags. + +properties: + compatible: + enum: + - mediatek,mt8516-eth + - mediatek,mt8518-eth + - mediatek,mt8175-eth + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + additionalItems: false + items: + - const: core + - const: reg + - const: trans + + mediatek,pericfg: + $ref: /schemas/types.yaml#definitions/phandle + description: + Phandle to the device containing the PERICFG register range. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - mediatek,pericfg + - phy-handle + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mt8516-clk.h> + + ethernet: ethernet@11180000 { + compatible = "mediatek,mt8516-eth"; + reg = <0 0x11180000 0 0x1000>; + mediatek,pericfg = <&pericfg>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_RG_ETH>, + <&topckgen CLK_TOP_66M_ETH>, + <&topckgen CLK_TOP_133M_ETH>; + clock-names = "core", "reg", "trans"; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; + };