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Fri, 23 Oct 2020 01:20:52 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 02:15:00 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 17:14:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Oct 2020 17:14:54 +0800 From: Miles Chen To: Catalin Marinas , Russell King , Minchan Kim Subject: [PATCH v2 4/4] arm: replace vector mem type with read-only type Date: Fri, 23 Oct 2020 17:14:37 +0800 Message-ID: <20201023091437.8225-5-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201023091437.8225-1-miles.chen@mediatek.com> References: <20201023091437.8225-1-miles.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: E8A464A3D2B693A78F39320912CA98801136E8EB1B1EEC0E5212E5D3E01CC5D02000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_052721_859403_97732250 X-CRM114-Status: GOOD ( 19.70 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, Miles Chen , linux-mediatek@lists.infradead.org, Suren Baghdasaryan , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Since kernel no longer writes to the vector, try to replace the vector mem type with read-only type and remove L_PTE_MT_VECTORS. from Catalin in [1]: " > I don't think this matters since the kernel no longer writes to the > vectors page at run-time but it needs cleaning up a bit (and testing in > case I missed something). IOW, do we still need a dedicated mapping type > for the vectors or we can simply use the read-only user page attributes? " [1] https://lore.kernel.org/patchwork/patch/986574/ Cc: Russell King Cc: Catalin Marinas Cc: Minchan Kim Cc: Suren Baghdasaryan Signed-off-by: Miles Chen --- arch/arm/include/asm/pgtable-2level.h | 1 - arch/arm/mm/mmu.c | 7 +++---- arch/arm/mm/proc-macros.S | 2 +- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index 385e7a32394e..438359d3675f 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -163,7 +163,6 @@ #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ -#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */ #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ #if defined(CONFIG_CPU_V7) || defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index ab69250a86bc..0b6b377e2cce 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -536,12 +536,11 @@ static void __init build_mem_type_table(void) #ifndef CONFIG_ARM_LPAE /* - * We don't use domains on ARMv6 (since this causes problems with - * v6/v7 kernels), so we must use a separate memory type for user - * r/o, kernel r/w to map the vectors page. + * We no longer write to the vector pages ar run-time, to + * use read-only user page attribute for vector. */ if (cpu_arch == CPU_ARCH_ARMv6) - vecs_pgprot |= L_PTE_MT_VECTORS; + vecs_pgprot |= L_PTE_RDONLY; /* * Check is it with support for the PXN bit diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index dde1d6374250..f3e6551b4a7e 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -137,7 +137,7 @@ .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS + .long 0x00 @ unused .long 0x00 @ L_PTE_MT_MINICACHE (not present) .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC .long 0x00 @ unused