| Message ID | 20201023133130.194140-3-fparent@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add DRM/DSI support for MT8167 SoC | expand |
Hi, Fabien: Fabien Parent <fparent@baylibre.com> 於 2020年10月23日 週五 下午9:31寫道： > > Add binding documentation for the MT8167 SoC. Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> In [1], Mediatek DPI binding document has been changed to yaml format, would you please also change this document to yaml? Ditto for mediatek,disp.txt. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20200917073305.25738-1-jitao.shi@mediatek.com/ Regards, Chun-Kuang. > > Signed-off-by: Fabien Parent <fparent@baylibre.com> > --- > > Changelog: > > V2: removed part that added a new clock > > .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > index f06f24d405a5..6a10de812158 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > @@ -7,7 +7,7 @@ channel output. > > Required properties: > - compatible: "mediatek,<chip>-dsi" > -- the supported chips are mt2701, mt7623, mt8173 and mt8183. > +- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. > - reg: Physical base address and length of the controller's registers > - interrupts: The interrupt signal from the function block. > - clocks: device clocks > @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. > > Required properties: > - compatible: "mediatek,<chip>-mipi-tx" > -- the supported chips are mt2701, 7623, mt8173 and mt8183. > +- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183. > - reg: Physical base address and length of the controller's registers > - clocks: PLL reference clock > - clock-output-names: name of the output clock line to the DSI encoder > -- > 2.28.0 >
Hi, Fabien: Fabien Parent <fparent@baylibre.com> 於 2020年10月23日 週五 下午9:31寫道： > > Add binding documentation for the MT8167 SoC. Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: Fabien Parent <fparent@baylibre.com> > --- > > Changelog: > > V2: removed part that added a new clock > > .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > index f06f24d405a5..6a10de812158 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > @@ -7,7 +7,7 @@ channel output. > > Required properties: > - compatible: "mediatek,<chip>-dsi" > -- the supported chips are mt2701, mt7623, mt8173 and mt8183. > +- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. > - reg: Physical base address and length of the controller's registers > - interrupts: The interrupt signal from the function block. > - clocks: device clocks > @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. > > Required properties: > - compatible: "mediatek,<chip>-mipi-tx" > -- the supported chips are mt2701, 7623, mt8173 and mt8183. > +- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183. > - reg: Physical base address and length of the controller's registers > - clocks: PLL reference clock > - clock-output-names: name of the output clock line to the DSI encoder > -- > 2.28.0 >
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index f06f24d405a5..6a10de812158 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -7,7 +7,7 @@ channel output. Required properties: - compatible: "mediatek,<chip>-dsi" -- the supported chips are mt2701, mt7623, mt8173 and mt8183. +- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. Required properties: - compatible: "mediatek,<chip>-mipi-tx" -- the supported chips are mt2701, 7623, mt8173 and mt8183. +- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - clocks: PLL reference clock - clock-output-names: name of the output clock line to the DSI encoder
Add binding documentation for the MT8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> --- Changelog: V2: removed part that added a new clock .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)