diff mbox series

[2/2] soc: mediatek: mmsys: Add support for MT8167 SoC

Message ID 20201027160631.608503-2-fparent@baylibre.com (mailing list archive)
State New, archived
Headers show
Series [1/2] dt-bindings: mediatek: mmsys: add mt1867 binding | expand

Commit Message

Fabien Parent Oct. 27, 2020, 4:06 p.m. UTC 
Add routing table for DSI on MT8167 SoC. The registers are mostly
incompatible with the current defines, so new one for MT8167 are added.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---

This patch depends on the patch series
"soc: mediatek: Prepare MMSYS for DDP routing using tables"

[0] https://lore.kernel.org/patchwork/cover/1317813/

 drivers/soc/mediatek/mtk-mmsys.c | 50 ++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

Comments

Matthias Brugger March 30, 2021, 9:15 a.m. UTC | #1 
Hi Fabien,

Sorry for taking so long on that patch.
Generally the patch looks good, but I just merged a small change how we add new
SoC to the driver.
Please see comments below.

On 27/10/2020 17:06, Fabien Parent wrote:
> Add routing table for DSI on MT8167 SoC. The registers are mostly
> incompatible with the current defines, so new one for MT8167 are added.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> 
> This patch depends on the patch series
> "soc: mediatek: Prepare MMSYS for DDP routing using tables"
> 
> [0] https://lore.kernel.org/patchwork/cover/1317813/
> 
>  drivers/soc/mediatek/mtk-mmsys.c | 50 ++++++++++++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index f00d6d08c9c5..9890990a74a9 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -85,6 +85,22 @@
>  #define DSI_SEL_IN_RDMA				0x1
>  #define DSI_SEL_IN_MASK				0x1
>  
> +/* MT8167 */
> +#define MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x030
> +#define MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN	0x038
> +#define MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x058
> +#define MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN		0x064
> +#define MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN	0x06c
> +
> +#define MT8167_DITHER_MOUT_EN_RDMA0			BIT(0)
> +#define MT8167_DITHER_MOUT_EN_MASK			0x7
> +
> +#define MT8167_RDMA0_SOUT_DSI0				0x2
> +#define MT8167_RDMA0_SOUT_MASK				0x3
> +
> +#define MT8167_DSI0_SEL_IN_RDMA0			0x1
> +#define MT8167_DSI0_SEL_IN_MASK				0x3
> +
>  struct mtk_mmsys_routes {
>  	u32 from_comp;
>  	u32 to_comp;
> @@ -124,6 +140,30 @@ struct mtk_mmsys {
>  	const struct mtk_mmsys_driver_data *data;
>  };
>  
> +static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {

Please put the defines and the routing table in a separate header file
mt8167-mmsys.h

Thanks and once again sorry for the inconvenience.
Matthias

> +	{
> +		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> +		MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
> +		OVL0_MOUT_EN_COLOR0, OVL0_MOUT_EN_COLOR0
> +	}, {
> +		DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
> +		MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN,
> +		MT8167_DITHER_MOUT_EN_MASK, MT8167_DITHER_MOUT_EN_RDMA0
> +	}, {
> +		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> +		MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
> +		COLOR0_SEL_IN_OVL0, COLOR0_SEL_IN_OVL0
> +	}, {
> +		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
> +		MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
> +		MT8167_DSI0_SEL_IN_MASK, MT8167_DSI0_SEL_IN_RDMA0
> +	}, {
> +		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
> +		MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN,
> +		MT8167_RDMA0_SOUT_MASK, MT8167_RDMA0_SOUT_DSI0
> +	},
> +};
> +
>  static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
>  	{
>  		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
> @@ -288,6 +328,12 @@ static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
>  	}
>  };
>  
> +static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
> +	.clk_driver = "clk-mt8167-mm",
> +	.routes = mt8167_mmsys_routing_table,
> +	.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
> +};
> +
>  static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>  	.clk_driver = "clk-mt8173-mm",
>  	.routes = mt8173_mmsys_routing_table,
> @@ -385,6 +431,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
>  		.compatible = "mediatek,mt6797-mmsys",
>  		.data = &mt6797_mmsys_driver_data,
>  	},
> +	{
> +		.compatible = "mediatek,mt8167-mmsys",
> +		.data = &mt8167_mmsys_driver_data,
> +	},
>  	{
>  		.compatible = "mediatek,mt8173-mmsys",
>  		.data = &mt8173_mmsys_driver_data,
>
diff mbox series

Patch

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index f00d6d08c9c5..9890990a74a9 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -85,6 +85,22 @@ 
 #define DSI_SEL_IN_RDMA				0x1
 #define DSI_SEL_IN_MASK				0x1
 
+/* MT8167 */
+#define MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x030
+#define MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN	0x038
+#define MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x058
+#define MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN		0x064
+#define MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN	0x06c
+
+#define MT8167_DITHER_MOUT_EN_RDMA0			BIT(0)
+#define MT8167_DITHER_MOUT_EN_MASK			0x7
+
+#define MT8167_RDMA0_SOUT_DSI0				0x2
+#define MT8167_RDMA0_SOUT_MASK				0x3
+
+#define MT8167_DSI0_SEL_IN_RDMA0			0x1
+#define MT8167_DSI0_SEL_IN_MASK				0x3
+
 struct mtk_mmsys_routes {
 	u32 from_comp;
 	u32 to_comp;
@@ -124,6 +140,30 @@  struct mtk_mmsys {
 	const struct mtk_mmsys_driver_data *data;
 };
 
+static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
+	{
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
+		MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
+		OVL0_MOUT_EN_COLOR0, OVL0_MOUT_EN_COLOR0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
+		MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN,
+		MT8167_DITHER_MOUT_EN_MASK, MT8167_DITHER_MOUT_EN_RDMA0
+	}, {
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
+		MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
+		COLOR0_SEL_IN_OVL0, COLOR0_SEL_IN_OVL0
+	}, {
+		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
+		MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
+		MT8167_DSI0_SEL_IN_MASK, MT8167_DSI0_SEL_IN_RDMA0
+	}, {
+		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
+		MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN,
+		MT8167_RDMA0_SOUT_MASK, MT8167_RDMA0_SOUT_DSI0
+	},
+};
+
 static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
 	{
 		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
@@ -288,6 +328,12 @@  static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
 	}
 };
 
+static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
+	.clk_driver = "clk-mt8167-mm",
+	.routes = mt8167_mmsys_routing_table,
+	.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
+};
+
 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.clk_driver = "clk-mt8173-mm",
 	.routes = mt8173_mmsys_routing_table,
@@ -385,6 +431,10 @@  static const struct of_device_id of_match_mtk_mmsys[] = {
 		.compatible = "mediatek,mt6797-mmsys",
 		.data = &mt6797_mmsys_driver_data,
 	},
+	{
+		.compatible = "mediatek,mt8167-mmsys",
+		.data = &mt8167_mmsys_driver_data,
+	},
 	{
 		.compatible = "mediatek,mt8173-mmsys",
 		.data = &mt8173_mmsys_driver_data,