diff mbox series

[v4,17/24] iommu/mediatek: Add single domain

Message ID 20201111123838.15682-18-yong.wu@mediatek.com (mailing list archive)
State New
Headers show
Series MT8192 IOMMU support | expand

Commit Message

Yong Wu Nov. 11, 2020, 12:38 p.m. UTC
Defaultly the iova range is 0-4G. here we add a single-domain(0-4G)
for the previous SoC. this also is a preparing patch for supporting
multi-domains.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
 drivers/iommu/mtk_iommu.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Robin Murphy Nov. 26, 2020, 5:11 p.m. UTC | #1
On 2020-11-11 12:38, Yong Wu wrote:
> Defaultly the iova range is 0-4G. here we add a single-domain(0-4G)
> for the previous SoC. this also is a preparing patch for supporting
> multi-domains.
> 
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
>   drivers/iommu/mtk_iommu.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index bf3f4e0f4748..a7727a3899d1 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -161,6 +161,10 @@ struct mtk_iommu_iova_region {
>   	unsigned long long	size;
>   };
>   
> +static const struct mtk_iommu_iova_region single_domain[] = {
> +	{.iova_base = 0,		.size = SZ_4G},
> +};

Hang on, given how the previous patch works, surely this means you're 
now going to *reserve* the entire address space? That doesn't seem 
right... :/

Robin.

> +
>   /*
>    * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
>    * for the performance.
> @@ -922,6 +926,8 @@ static const struct mtk_iommu_plat_data mt2712_data = {
>   	.m4u_plat     = M4U_MT2712,
>   	.flags        = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
>   	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
> +	.iova_region  = single_domain,
> +	.iova_region_nr = ARRAY_SIZE(single_domain),
>   	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
>   };
>   
> @@ -929,6 +935,8 @@ static const struct mtk_iommu_plat_data mt6779_data = {
>   	.m4u_plat      = M4U_MT6779,
>   	.flags         = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN,
>   	.inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
> +	.iova_region   = single_domain,
> +	.iova_region_nr = ARRAY_SIZE(single_domain),
>   	.larbid_remap  = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
>   };
>   
> @@ -944,6 +952,8 @@ static const struct mtk_iommu_plat_data mt8173_data = {
>   	.flags	      = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
>   			HAS_LEGACY_IVRP_PADDR,
>   	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
> +	.iova_region  = single_domain,
> +	.iova_region_nr = ARRAY_SIZE(single_domain),
>   	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
>   };
>   
> @@ -951,6 +961,8 @@ static const struct mtk_iommu_plat_data mt8183_data = {
>   	.m4u_plat     = M4U_MT8183,
>   	.flags        = RESET_AXI,
>   	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
> +	.iova_region  = single_domain,
> +	.iova_region_nr = ARRAY_SIZE(single_domain),
>   	.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
>   };
>   
>
Yong Wu Nov. 27, 2020, 6:21 a.m. UTC | #2
On Thu, 2020-11-26 at 17:11 +0000, Robin Murphy wrote:
> On 2020-11-11 12:38, Yong Wu wrote:
> > Defaultly the iova range is 0-4G. here we add a single-domain(0-4G)
> > for the previous SoC. this also is a preparing patch for supporting
> > multi-domains.
> > 
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> >   drivers/iommu/mtk_iommu.c | 12 ++++++++++++
> >   1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index bf3f4e0f4748..a7727a3899d1 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -161,6 +161,10 @@ struct mtk_iommu_iova_region {
> >   	unsigned long long	size;
> >   };
> >   
> > +static const struct mtk_iommu_iova_region single_domain[] = {
> > +	{.iova_base = 0,		.size = SZ_4G},
> > +};
> 
> Hang on, given how the previous patch works, surely this means you're 
> now going to *reserve* the entire address space? That doesn't seem 
> right... :/

Could you help share more? in which case it is not right?

In the code:
domain->geometry.aperture_end = iova_base + size - 1. 

this is same with DMA_BIT_MASK(32). It looks don't change anything.

> 
> Robin.
> 
> > +
> >   /*
> >    * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
> >    * for the performance.
> > @@ -922,6 +926,8 @@ static const struct mtk_iommu_plat_data mt2712_data = {
> >   	.m4u_plat     = M4U_MT2712,
> >   	.flags        = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
> >   	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
> > +	.iova_region  = single_domain,
> > +	.iova_region_nr = ARRAY_SIZE(single_domain),
> >   	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
> >   };
> >   
> > @@ -929,6 +935,8 @@ static const struct mtk_iommu_plat_data mt6779_data = {
> >   	.m4u_plat      = M4U_MT6779,
> >   	.flags         = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN,
> >   	.inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
> > +	.iova_region   = single_domain,
> > +	.iova_region_nr = ARRAY_SIZE(single_domain),
> >   	.larbid_remap  = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
> >   };
> >   
> > @@ -944,6 +952,8 @@ static const struct mtk_iommu_plat_data mt8173_data = {
> >   	.flags	      = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
> >   			HAS_LEGACY_IVRP_PADDR,
> >   	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
> > +	.iova_region  = single_domain,
> > +	.iova_region_nr = ARRAY_SIZE(single_domain),
> >   	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
> >   };
> >   
> > @@ -951,6 +961,8 @@ static const struct mtk_iommu_plat_data mt8183_data = {
> >   	.m4u_plat     = M4U_MT8183,
> >   	.flags        = RESET_AXI,
> >   	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
> > +	.iova_region  = single_domain,
> > +	.iova_region_nr = ARRAY_SIZE(single_domain),
> >   	.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
> >   };
> >   
> >
diff mbox series

Patch

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index bf3f4e0f4748..a7727a3899d1 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -161,6 +161,10 @@  struct mtk_iommu_iova_region {
 	unsigned long long	size;
 };
 
+static const struct mtk_iommu_iova_region single_domain[] = {
+	{.iova_base = 0,		.size = SZ_4G},
+};
+
 /*
  * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
  * for the performance.
@@ -922,6 +926,8 @@  static const struct mtk_iommu_plat_data mt2712_data = {
 	.m4u_plat     = M4U_MT2712,
 	.flags        = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
 	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
+	.iova_region  = single_domain,
+	.iova_region_nr = ARRAY_SIZE(single_domain),
 	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
 };
 
@@ -929,6 +935,8 @@  static const struct mtk_iommu_plat_data mt6779_data = {
 	.m4u_plat      = M4U_MT6779,
 	.flags         = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN,
 	.inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
+	.iova_region   = single_domain,
+	.iova_region_nr = ARRAY_SIZE(single_domain),
 	.larbid_remap  = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
 };
 
@@ -944,6 +952,8 @@  static const struct mtk_iommu_plat_data mt8173_data = {
 	.flags	      = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
 			HAS_LEGACY_IVRP_PADDR,
 	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
+	.iova_region  = single_domain,
+	.iova_region_nr = ARRAY_SIZE(single_domain),
 	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
 };
 
@@ -951,6 +961,8 @@  static const struct mtk_iommu_plat_data mt8183_data = {
 	.m4u_plat     = M4U_MT8183,
 	.flags        = RESET_AXI,
 	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
+	.iova_region  = single_domain,
+	.iova_region_nr = ARRAY_SIZE(single_domain),
 	.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
 };