diff mbox series

remoteproc/mediatek: change MT8192 CFG register base

Message ID 20201210054109.587795-1-tzungbi@google.com (mailing list archive)
State New
Headers show
Series remoteproc/mediatek: change MT8192 CFG register base | expand

Commit Message

Tzung-Bi Shih Dec. 10, 2020, 5:41 a.m. UTC
The correct MT8192 CFG register base is 0x20000 off.  Changes the
registers accordingly.

Fixes: fd0b6c1ff85a ("remoteproc/mediatek: Add support for mt8192 SCP")
Signed-off-by: Tzung-Bi Shih <tzungbi@google.com>
---
 drivers/remoteproc/mtk_common.h | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

Comments

Bjorn Andersson Dec. 10, 2020, 5:02 p.m. UTC | #1
On Wed 09 Dec 23:41 CST 2020, Tzung-Bi Shih wrote:

> The correct MT8192 CFG register base is 0x20000 off.  Changes the
> registers accordingly.
> 
> Fixes: fd0b6c1ff85a ("remoteproc/mediatek: Add support for mt8192 SCP")
> Signed-off-by: Tzung-Bi Shih <tzungbi@google.com>

I presume there's an associated DT change with this?

I'm okay with taking this, but would like to have Matthias ack on the
fact that we're breaking backwards compatibility with older DTS.

(Or I could ack this and Matthias can take it together with the DT
change, to reduce the breakage gap in the git history?)

Regards,
Bjorn

> ---
>  drivers/remoteproc/mtk_common.h | 26 +++++++++++++-------------
>  1 file changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
> index b3397d327786..fb022ff93dc1 100644
> --- a/drivers/remoteproc/mtk_common.h
> +++ b/drivers/remoteproc/mtk_common.h
> @@ -32,22 +32,22 @@
>  #define MT8183_SCP_CACHESIZE_8KB	BIT(8)
>  #define MT8183_SCP_CACHE_CON_WAYEN	BIT(10)
>  
> -#define MT8192_L2TCM_SRAM_PD_0		0x210C0
> -#define MT8192_L2TCM_SRAM_PD_1		0x210C4
> -#define MT8192_L2TCM_SRAM_PD_2		0x210C8
> -#define MT8192_L1TCM_SRAM_PDN		0x2102C
> -#define MT8192_CPU0_SRAM_PD		0x21080
> -
> -#define MT8192_SCP2APMCU_IPC_SET	0x24080
> -#define MT8192_SCP2APMCU_IPC_CLR	0x24084
> +#define MT8192_L2TCM_SRAM_PD_0		0x10C0
> +#define MT8192_L2TCM_SRAM_PD_1		0x10C4
> +#define MT8192_L2TCM_SRAM_PD_2		0x10C8
> +#define MT8192_L1TCM_SRAM_PDN		0x102C
> +#define MT8192_CPU0_SRAM_PD		0x1080
> +
> +#define MT8192_SCP2APMCU_IPC_SET	0x4080
> +#define MT8192_SCP2APMCU_IPC_CLR	0x4084
>  #define MT8192_SCP_IPC_INT_BIT		BIT(0)
> -#define MT8192_SCP2SPM_IPC_CLR		0x24094
> -#define MT8192_GIPC_IN_SET		0x24098
> +#define MT8192_SCP2SPM_IPC_CLR		0x4094
> +#define MT8192_GIPC_IN_SET		0x4098
>  #define MT8192_HOST_IPC_INT_BIT		BIT(0)
>  
> -#define MT8192_CORE0_SW_RSTN_CLR	0x30000
> -#define MT8192_CORE0_SW_RSTN_SET	0x30004
> -#define MT8192_CORE0_WDT_CFG		0x30034
> +#define MT8192_CORE0_SW_RSTN_CLR	0x10000
> +#define MT8192_CORE0_SW_RSTN_SET	0x10004
> +#define MT8192_CORE0_WDT_CFG		0x10034
>  
>  #define SCP_FW_VER_LEN			32
>  #define SCP_SHARE_BUFFER_SIZE		288
> -- 
> 2.29.2.576.ga3fc446d84-goog
>
Tzung-Bi Shih Dec. 10, 2020, 5:09 p.m. UTC | #2
On Fri, Dec 11, 2020 at 1:02 AM Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
>
> On Wed 09 Dec 23:41 CST 2020, Tzung-Bi Shih wrote:
>
> > The correct MT8192 CFG register base is 0x20000 off.  Changes the
> > registers accordingly.
> >
> > Fixes: fd0b6c1ff85a ("remoteproc/mediatek: Add support for mt8192 SCP")
> > Signed-off-by: Tzung-Bi Shih <tzungbi@google.com>
>
> I presume there's an associated DT change with this?
>
> I'm okay with taking this, but would like to have Matthias ack on the
> fact that we're breaking backwards compatibility with older DTS.
>
> (Or I could ack this and Matthias can take it together with the DT
> change, to reduce the breakage gap in the git history?)

Yes, it has associated DT changes.  But the board "MT8192 SCP" is
still under development, the DTS part hasn't been sent to upstream
yet.

Thus, it won't break anyone else.
Bjorn Andersson Dec. 10, 2020, 7:13 p.m. UTC | #3
On Thu 10 Dec 11:09 CST 2020, Tzung-Bi Shih wrote:

> On Fri, Dec 11, 2020 at 1:02 AM Bjorn Andersson
> <bjorn.andersson@linaro.org> wrote:
> >
> > On Wed 09 Dec 23:41 CST 2020, Tzung-Bi Shih wrote:
> >
> > > The correct MT8192 CFG register base is 0x20000 off.  Changes the
> > > registers accordingly.
> > >
> > > Fixes: fd0b6c1ff85a ("remoteproc/mediatek: Add support for mt8192 SCP")
> > > Signed-off-by: Tzung-Bi Shih <tzungbi@google.com>
> >
> > I presume there's an associated DT change with this?
> >
> > I'm okay with taking this, but would like to have Matthias ack on the
> > fact that we're breaking backwards compatibility with older DTS.
> >
> > (Or I could ack this and Matthias can take it together with the DT
> > change, to reduce the breakage gap in the git history?)
> 
> Yes, it has associated DT changes.  But the board "MT8192 SCP" is
> still under development, the DTS part hasn't been sent to upstream
> yet.
> 
> Thus, it won't break anyone else.

Then I don't mind merging this, will include it in v5.11.

Thank you,
Bjorn
diff mbox series

Patch

diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
index b3397d327786..fb022ff93dc1 100644
--- a/drivers/remoteproc/mtk_common.h
+++ b/drivers/remoteproc/mtk_common.h
@@ -32,22 +32,22 @@ 
 #define MT8183_SCP_CACHESIZE_8KB	BIT(8)
 #define MT8183_SCP_CACHE_CON_WAYEN	BIT(10)
 
-#define MT8192_L2TCM_SRAM_PD_0		0x210C0
-#define MT8192_L2TCM_SRAM_PD_1		0x210C4
-#define MT8192_L2TCM_SRAM_PD_2		0x210C8
-#define MT8192_L1TCM_SRAM_PDN		0x2102C
-#define MT8192_CPU0_SRAM_PD		0x21080
-
-#define MT8192_SCP2APMCU_IPC_SET	0x24080
-#define MT8192_SCP2APMCU_IPC_CLR	0x24084
+#define MT8192_L2TCM_SRAM_PD_0		0x10C0
+#define MT8192_L2TCM_SRAM_PD_1		0x10C4
+#define MT8192_L2TCM_SRAM_PD_2		0x10C8
+#define MT8192_L1TCM_SRAM_PDN		0x102C
+#define MT8192_CPU0_SRAM_PD		0x1080
+
+#define MT8192_SCP2APMCU_IPC_SET	0x4080
+#define MT8192_SCP2APMCU_IPC_CLR	0x4084
 #define MT8192_SCP_IPC_INT_BIT		BIT(0)
-#define MT8192_SCP2SPM_IPC_CLR		0x24094
-#define MT8192_GIPC_IN_SET		0x24098
+#define MT8192_SCP2SPM_IPC_CLR		0x4094
+#define MT8192_GIPC_IN_SET		0x4098
 #define MT8192_HOST_IPC_INT_BIT		BIT(0)
 
-#define MT8192_CORE0_SW_RSTN_CLR	0x30000
-#define MT8192_CORE0_SW_RSTN_SET	0x30004
-#define MT8192_CORE0_WDT_CFG		0x30034
+#define MT8192_CORE0_SW_RSTN_CLR	0x10000
+#define MT8192_CORE0_SW_RSTN_SET	0x10004
+#define MT8192_CORE0_WDT_CFG		0x10034
 
 #define SCP_FW_VER_LEN			32
 #define SCP_SHARE_BUFFER_SIZE		288