diff mbox series

[v4,4/8] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase

Message ID 20210129073436.2429834-5-hsinyi@chromium.org (mailing list archive)
State New
Headers show
Series drm/mediatek: add support for mediatek SOC MT8192 | expand

Commit Message

Hsin-Yi Wang Jan. 29, 2021, 7:34 a.m. UTC
From: Yongqiang Niu <yongqiang.niu@mediatek.com>

enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch,
ovl will hang up when more than 1 layer enabled.

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

Comments

CK Hu Jan. 29, 2021, 8:21 a.m. UTC | #1
Hi, Hsin-Yi:

On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
> 
> enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch,
> ovl will hang up when more than 1 layer enabled.

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index da7e38a28759b..961f87f8d4d15 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -24,6 +24,7 @@
>  #define DISP_REG_OVL_RST			0x0014
>  #define DISP_REG_OVL_ROI_SIZE			0x0020
>  #define DISP_REG_OVL_DATAPATH_CON		0x0024
> +#define OVL_LAYER_SMI_ID_EN				BIT(0)
>  #define OVL_BGCLR_SEL_IN				BIT(2)
>  #define DISP_REG_OVL_ROI_BGCLR			0x0028
>  #define DISP_REG_OVL_SRC_CON			0x002c
> @@ -62,6 +63,7 @@ struct mtk_disp_ovl_data {
>  	unsigned int gmc_bits;
>  	unsigned int layer_nr;
>  	bool fmt_rgb565_is_0;
> +	bool smi_id_en;
>  };
>  
>  /**
> @@ -134,6 +136,13 @@ void mtk_ovl_start(struct device *dev)
>  {
>  	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
>  
> +	if (ovl->data->smi_id_en) {
> +		unsigned int reg;
> +
> +		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> +		reg = reg | OVL_LAYER_SMI_ID_EN;
> +		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> +	}
>  	writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
>  }
>  
> @@ -142,6 +151,14 @@ void mtk_ovl_stop(struct device *dev)
>  	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
>  
>  	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
> +	if (ovl->data->smi_id_en) {
> +		unsigned int reg;
> +
> +		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> +		reg = reg & ~OVL_LAYER_SMI_ID_EN;
> +		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> +	}
> +
>  }
>  
>  void mtk_ovl_config(struct device *dev, unsigned int w,
Chun-Kuang Hu Jan. 31, 2021, 3:56 a.m. UTC | #2
Hi, Hsin-Yi:

CK Hu <ck.hu@mediatek.com> 於 2021年1月29日 週五 下午4:21寫道:
>
> Hi, Hsin-Yi:
>
> On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> > From: Yongqiang Niu <yongqiang.niu@mediatek.com>
> >
> > enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch,
> > ovl will hang up when more than 1 layer enabled.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang.

>
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > index da7e38a28759b..961f87f8d4d15 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -24,6 +24,7 @@
> >  #define DISP_REG_OVL_RST                     0x0014
> >  #define DISP_REG_OVL_ROI_SIZE                        0x0020
> >  #define DISP_REG_OVL_DATAPATH_CON            0x0024
> > +#define OVL_LAYER_SMI_ID_EN                          BIT(0)
> >  #define OVL_BGCLR_SEL_IN                             BIT(2)
> >  #define DISP_REG_OVL_ROI_BGCLR                       0x0028
> >  #define DISP_REG_OVL_SRC_CON                 0x002c
> > @@ -62,6 +63,7 @@ struct mtk_disp_ovl_data {
> >       unsigned int gmc_bits;
> >       unsigned int layer_nr;
> >       bool fmt_rgb565_is_0;
> > +     bool smi_id_en;
> >  };
> >
> >  /**
> > @@ -134,6 +136,13 @@ void mtk_ovl_start(struct device *dev)
> >  {
> >       struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
> >
> > +     if (ovl->data->smi_id_en) {
> > +             unsigned int reg;
> > +
> > +             reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> > +             reg = reg | OVL_LAYER_SMI_ID_EN;
> > +             writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> > +     }
> >       writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
> >  }
> >
> > @@ -142,6 +151,14 @@ void mtk_ovl_stop(struct device *dev)
> >       struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
> >
> >       writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
> > +     if (ovl->data->smi_id_en) {
> > +             unsigned int reg;
> > +
> > +             reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> > +             reg = reg & ~OVL_LAYER_SMI_ID_EN;
> > +             writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> > +     }
> > +
> >  }
> >
> >  void mtk_ovl_config(struct device *dev, unsigned int w,
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff mbox series

Patch

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index da7e38a28759b..961f87f8d4d15 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -24,6 +24,7 @@ 
 #define DISP_REG_OVL_RST			0x0014
 #define DISP_REG_OVL_ROI_SIZE			0x0020
 #define DISP_REG_OVL_DATAPATH_CON		0x0024
+#define OVL_LAYER_SMI_ID_EN				BIT(0)
 #define OVL_BGCLR_SEL_IN				BIT(2)
 #define DISP_REG_OVL_ROI_BGCLR			0x0028
 #define DISP_REG_OVL_SRC_CON			0x002c
@@ -62,6 +63,7 @@  struct mtk_disp_ovl_data {
 	unsigned int gmc_bits;
 	unsigned int layer_nr;
 	bool fmt_rgb565_is_0;
+	bool smi_id_en;
 };
 
 /**
@@ -134,6 +136,13 @@  void mtk_ovl_start(struct device *dev)
 {
 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 
+	if (ovl->data->smi_id_en) {
+		unsigned int reg;
+
+		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
+		reg = reg | OVL_LAYER_SMI_ID_EN;
+		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
+	}
 	writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
 }
 
@@ -142,6 +151,14 @@  void mtk_ovl_stop(struct device *dev)
 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 
 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
+	if (ovl->data->smi_id_en) {
+		unsigned int reg;
+
+		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
+		reg = reg & ~OVL_LAYER_SMI_ID_EN;
+		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
+	}
+
 }
 
 void mtk_ovl_config(struct device *dev, unsigned int w,