diff mbox series

[v13,6/8] drm/mediatek: enable dither function

Message ID 20210129092209.2584718-7-hsinyi@chromium.org (mailing list archive)
State New
Headers show
Series drm/mediatek: add support for mediatek SOC MT8183 | expand

Commit Message

Hsin-Yi Wang Jan. 29, 2021, 9:22 a.m. UTC
From: Yongqiang Niu <yongqiang.niu@mediatek.com>

Enable dither function to improve the display quality for dither
supported bpc 4, 6, 8. For not supported bpc, use relay mode.

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

Comments

Chun-Kuang Hu Jan. 31, 2021, 3:39 a.m. UTC | #1
Hi, Hsin-Yi:

Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年1月29日 週五 下午5:23寫道:
>
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> Enable dither function to improve the display quality for dither
> supported bpc 4, 6, 8. For not supported bpc, use relay mode.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index ac2cb25620357..5761dd15eedf2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -53,6 +53,7 @@
>  #define DITHER_EN                              BIT(0)
>  #define DISP_DITHER_CFG                                0x0020
>  #define DITHER_RELAY_MODE                      BIT(0)
> +#define DITHER_ENGINE_EN                       BIT(1)
>  #define DISP_DITHER_SIZE                       0x0030
>
>  #define LUT_10BIT_MASK                         0x03ff
> @@ -314,9 +315,17 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
>                               unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> -       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
> -       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> +       bool valid_bpc = (bpc == 4 || bpc == 6 || bpc == 8);
> +
> +       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_DITHER_SIZE);
> +       if (valid_bpc)
> +               mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> +                                     DISP_DITHER_CFG, DITHER_ENGINE_EN,
> +                                     cmdq_pkt);
> +       else
> +               mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg,
> +                             priv->regs, DISP_DITHER_CFG);

od has relay mode,

static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
  unsigned int h, unsigned int vrefresh,
  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE);
mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG);
mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt);
}

and it does not check valid bpc (I think drm core already set bpc to
4, 6, 8 or 0), so align implementation of mtk_dither_config() with
mtk_od_config().
gamma also has relay mode (refer to [1] page 689), but we need to
enable gamma's gamma function, so we do not set gamma to relay mode.
So I think maybe we could implement mtk_dither_config() as:

mtk_dither_config()
{
        mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg,
priv->regs, DISP_DITHER_SIZE);
        mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg,
priv->regs, DISP_DITHER_CFG);
        mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
DISP_DITHER_CFG, DITHER_ENGINE_EN, cmdq_pkt);
}

[1] https://www.96boards.org/documentation/consumer/mediatekx20/additional-docs/docs/MT6797_Register_Table_Part_2.pdf

Regards,
Chun-Kuang.

>  }
>
>  static void mtk_dither_start(struct device *dev)
> --
> 2.30.0.365.g02bc693789-goog
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hsin-Yi Wang Jan. 31, 2021, 5:12 a.m. UTC | #2
On Sun, Jan 31, 2021 at 11:40 AM Chun-Kuang Hu <chunkuang.hu@kernel.org> wrote:
>
> Hi, Hsin-Yi:
>
> Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年1月29日 週五 下午5:23寫道:
> >
> > From: Yongqiang Niu <yongqiang.niu@mediatek.com>
> >
> > Enable dither function to improve the display quality for dither
> > supported bpc 4, 6, 8. For not supported bpc, use relay mode.
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 ++++++++++++---
> >  1 file changed, 12 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index ac2cb25620357..5761dd15eedf2 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -53,6 +53,7 @@
> >  #define DITHER_EN                              BIT(0)
> >  #define DISP_DITHER_CFG                                0x0020
> >  #define DITHER_RELAY_MODE                      BIT(0)
> > +#define DITHER_ENGINE_EN                       BIT(1)
> >  #define DISP_DITHER_SIZE                       0x0030
> >
> >  #define LUT_10BIT_MASK                         0x03ff
> > @@ -314,9 +315,17 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
> >                               unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > -       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
> > -       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> > +       bool valid_bpc = (bpc == 4 || bpc == 6 || bpc == 8);
> > +
> > +       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> > +                     DISP_DITHER_SIZE);
> > +       if (valid_bpc)
> > +               mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > +                                     DISP_DITHER_CFG, DITHER_ENGINE_EN,
> > +                                     cmdq_pkt);
> > +       else
> > +               mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg,
> > +                             priv->regs, DISP_DITHER_CFG);
>
> od has relay mode,
>
> static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
>   unsigned int h, unsigned int vrefresh,
>   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE);
> mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG);
> mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt);
> }
>
> and it does not check valid bpc (I think drm core already set bpc to
> 4, 6, 8 or 0), so align implementation of mtk_dither_config() with
> mtk_od_config().
> gamma also has relay mode (refer to [1] page 689), but we need to
> enable gamma's gamma function, so we do not set gamma to relay mode.
> So I think maybe we could implement mtk_dither_config() as:
>
> mtk_dither_config()
> {
>         mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg,
> priv->regs, DISP_DITHER_SIZE);
>         mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg,
> priv->regs, DISP_DITHER_CFG);
>         mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> DISP_DITHER_CFG, DITHER_ENGINE_EN, cmdq_pkt);
> }
>
> [1] https://www.96boards.org/documentation/consumer/mediatekx20/additional-docs/docs/MT6797_Register_Table_Part_2.pdf
>
> Regards,
> Chun-Kuang.
>
Hi CK,

I send the patch here:
https://patchwork.kernel.org/project/linux-mediatek/patch/20210131051058.3407985-1-hsinyi@chromium.org/
as others are already merged to the tree.

Thanks

> >  }
> >
> >  static void mtk_dither_start(struct device *dev)
> > --
> > 2.30.0.365.g02bc693789-goog
> >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
diff mbox series

Patch

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index ac2cb25620357..5761dd15eedf2 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -53,6 +53,7 @@ 
 #define DITHER_EN				BIT(0)
 #define DISP_DITHER_CFG				0x0020
 #define DITHER_RELAY_MODE			BIT(0)
+#define DITHER_ENGINE_EN			BIT(1)
 #define DISP_DITHER_SIZE			0x0030
 
 #define LUT_10BIT_MASK				0x03ff
@@ -314,9 +315,17 @@  static void mtk_dither_config(struct device *dev, unsigned int w,
 			      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
-	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
-	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
+	bool valid_bpc = (bpc == 4 || bpc == 6 || bpc == 8);
+
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_DITHER_SIZE);
+	if (valid_bpc)
+		mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
+				      DISP_DITHER_CFG, DITHER_ENGINE_EN,
+				      cmdq_pkt);
+	else
+		mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg,
+			      priv->regs, DISP_DITHER_CFG);
 }
 
 static void mtk_dither_start(struct device *dev)