| Message ID | 20210525121448.30075-3-rex-bc.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mt8183 dpi supports dual edge | expand |
Hi, Rex: Rex-BC Chen <rex-bc.chen@mediatek.com> 於 2021年5月25日 週二 下午8:15寫道： > > Add output_fmts and num_output_fmts value for all configuration. > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > index d3b883c97aaf..d6a422986efc 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -695,10 +695,21 @@ static unsigned int mt8183_calculate_factor(int clock) > return 2; > } > > +static const u32 mt8173_output_fmts[] = { > +MEDIA_BUS_FMT_RGB888_1X24, indent. > +}; > + > +static const u32 mt8183_output_fmts[] = { > +MEDIA_BUS_FMT_RGB888_2X12_LE, > +MEDIA_BUS_FMT_RGB888_2X12_BE, ditto. Regards, Chun-Kuang. > +}; > + > static const struct mtk_dpi_conf mt8173_conf = { > .cal_factor = mt8173_calculate_factor, > .reg_h_fre_con = 0xe0, > .max_clock_khz = 300000, > + .output_fmts = mt8173_output_fmts, > + .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > }; > > static const struct mtk_dpi_conf mt2701_conf = { > @@ -706,18 +717,24 @@ static const struct mtk_dpi_conf mt2701_conf = { > .reg_h_fre_con = 0xb0, > .edge_sel_en = true, > .max_clock_khz = 150000, > + .output_fmts = mt8173_output_fmts, > + .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > }; > > static const struct mtk_dpi_conf mt8183_conf = { > .cal_factor = mt8183_calculate_factor, > .reg_h_fre_con = 0xe0, > .max_clock_khz = 100000, > + .output_fmts = mt8183_output_fmts, > + .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), > }; > > static const struct mtk_dpi_conf mt8192_conf = { > .cal_factor = mt8183_calculate_factor, > .reg_h_fre_con = 0xe0, > .max_clock_khz = 150000, > + .output_fmts = mt8173_output_fmts, > + .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > }; > > static int mtk_dpi_probe(struct platform_device *pdev) > -- > 2.18.0 >
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index d3b883c97aaf..d6a422986efc 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -695,10 +695,21 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; } +static const u32 mt8173_output_fmts[] = { +MEDIA_BUS_FMT_RGB888_1X24, +}; + +static const u32 mt8183_output_fmts[] = { +MEDIA_BUS_FMT_RGB888_2X12_LE, +MEDIA_BUS_FMT_RGB888_2X12_BE, +}; + static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, .max_clock_khz = 300000, + .output_fmts = mt8173_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), }; static const struct mtk_dpi_conf mt2701_conf = { @@ -706,18 +717,24 @@ static const struct mtk_dpi_conf mt2701_conf = { .reg_h_fre_con = 0xb0, .edge_sel_en = true, .max_clock_khz = 150000, + .output_fmts = mt8173_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), }; static const struct mtk_dpi_conf mt8183_conf = { .cal_factor = mt8183_calculate_factor, .reg_h_fre_con = 0xe0, .max_clock_khz = 100000, + .output_fmts = mt8183_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), }; static const struct mtk_dpi_conf mt8192_conf = { .cal_factor = mt8183_calculate_factor, .reg_h_fre_con = 0xe0, .max_clock_khz = 150000, + .output_fmts = mt8173_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), }; static int mtk_dpi_probe(struct platform_device *pdev)