[10/22] clk: mediatek: Add MT8195 ipesys clock support

Commit Message

Chun-Jie Chen June 16, 2021, 10:47 p.m. UTC

Add MT8195 ipesys clock provider

Signed-off-by: Chun-Jie Chen <[e-mail]>
---
 drivers/clk/mediatek/Kconfig          |  6 +++
 drivers/clk/mediatek/Makefile         |  1 +
 drivers/clk/mediatek/clk-mt8195-ipe.c | 53 +++++++++++++++++++++++++++
 3 files changed, 60 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-ipe.c

Comments

Chen-Yu Tsai July 6, 2021, 9:11 a.m. UTC | #1

On Thu, Jun 17, 2021 at 7:08 AM Chun-Jie Chen
<[e-mail]> wrote:
>
> Add MT8195 ipesys clock provider

It would be better if you could provide some more context for the patch,
such as what hardware subsystem / group does this belong to, what do
these clocks feed into? And in the case of supporting multiple clock
controllers in one driver, what led you to group them in the same
driver?

This applies to all your patches. The single statement "Add xxx clock
provider" is simply repeating what the subject already says.

The code looks OK.

Thanks
ChenYu

> Signed-off-by: Chun-Jie Chen <[e-mail]>

Patch

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index f92d0b6b7eec..ef7d4b433eee 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -618,6 +618,12 @@  config COMMON_CLK_MT8195_IMGSYS
 	help
 	  This driver supports MediaTek MT8195 imgsys clocks.
 
+config COMMON_CLK_MT8195_IPESYS
+	bool "Clock driver for MediaTek MT8195 ipesys"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 ipesys clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 1768eda917c2..991a9be7ac46 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -86,5 +86,6 @@  obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS_SRC) += clk-mt8195-aud_src.o
 obj-$(CONFIG_COMMON_CLK_MT8195_CAMSYS) += clk-mt8195-cam.o
 obj-$(CONFIG_COMMON_CLK_MT8195_CCUSYS) += clk-mt8195-ccu.o
 obj-$(CONFIG_COMMON_CLK_MT8195_IMGSYS) += clk-mt8195-img.o
+obj-$(CONFIG_COMMON_CLK_MT8195_IPESYS) += clk-mt8195-ipe.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-ipe.c b/drivers/clk/mediatek/clk-mt8195-ipe.c
new file mode 100644
index 000000000000..d63d7448591a
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-ipe.c
@@ -0,0 +1,53 @@ 
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <[e-mail]>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs ipe_cg_regs = {
+	.set_ofs = 0x0,
+	.clr_ofs = 0x0,
+	.sta_ofs = 0x0,
+};
+
+#define GATE_IPE(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
+
+static const struct mtk_gate ipe_clks[] = {
+	GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 0),
+	GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "ipe_sel", 1),
+	GATE_IPE(CLK_IPE_ME, "ipe_me", "ipe_sel", 2),
+	GATE_IPE(CLK_IPE_TOP, "ipe_top", "ipe_sel", 3),
+	GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "ipe_sel", 4),
+};
+
+static const struct mtk_clk_desc ipe_desc = {
+	.clks = ipe_clks,
+	.num_clks = ARRAY_SIZE(ipe_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_ipe[] = {
+	{
+		.compatible = "mediatek,mt8195-ipesys",
+		.data = &ipe_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_ipe_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-ipe",
+		.of_match_table = of_match_clk_mt8195_ipe,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_ipe_drv);