diff mbox series

[v1,2/3] dt-binding: mt8195: add toprgu reset-controller head file

Message ID 20210620134954.15233-3-Christine.Zhu@mediatek.com (mailing list archive)
State New, archived
Headers show
Series watchdog: mt8195: add wdt support | expand

Commit Message

Christine Zhu June 20, 2021, 1:49 p.m. UTC 
From: "christine.zhu" <Christine.Zhu@mediatek.com>

add toprgu reset-controller head file for MT8195 platform

Change-Id: Ib08da609e87d31ff0aa06b066f9797070931a693
Signed-off-by: christine.zhu <Christine.Zhu@mediatek.com>
---
 include/dt-bindings/reset/mt8195-resets.h | 29 +++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 include/dt-bindings/reset/mt8195-resets.h

Comments

Tzung-Bi Shih June 21, 2021, 6:11 a.m. UTC | #1 
On Sun, Jun 20, 2021 at 9:50 PM Christine Zhu
<Christine.Zhu@mediatek.com> wrote:
> add toprgu reset-controller head file for MT8195 platform
Please write complete sentences.

> Change-Id: Ib08da609e87d31ff0aa06b066f9797070931a693
Remove the unneeded tag.

> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2020 MediaTek Inc.
Maybe 2021?

The patch needs other proper prefixes.  For example, "dt-bindings:
reset: mt8195".
diff mbox series

Patch

diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
new file mode 100644
index 000000000000..620a594ee743
--- /dev/null
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -0,0 +1,29 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Crystal Guo <crystal.guo@mediatek.com>
+ */
+ 
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8195
+
+#define MT8195_TOPRGU_CONN_MCU_SW_RST          0
+#define MT8195_TOPRGU_INFRA_GRST_SW_RST        1
+#define MT8195_TOPRGU_APU_SW_RST               2
+#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST     6
+#define MT8195_TOPRGU_MMSYS_SW_RST             7
+#define MT8195_TOPRGU_MFG_SW_RST               8
+#define MT8195_TOPRGU_VENC_SW_RST              9
+#define MT8195_TOPRGU_VDEC_SW_RST              10
+#define MT8195_TOPRGU_IMG_SW_RST               11
+#define MT8195_TOPRGU_APMIXEDSYS_SW_RST        13
+#define MT8195_TOPRGU_AUDIO_SW_RST             14
+#define MT8195_TOPRGU_CAMSYS_SW_RST            15
+#define MT8195_TOPRGU_EDPTX_SW_RST             16
+#define MT8195_TOPRGU_ADSPSYS_SW_RST           21
+#define MT8195_TOPRGU_DPTX_SW_RST              22
+#define MT8195_TOPRGU_SPMI_MST_SW_RST          23
+
+#define MT8195_TOPRGU_SW_RST_NUM               16
+
+#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */