@@ -156,6 +156,10 @@ properties:
- enum:
- mediatek,mt8183-disp-gamma
+ # DSC: see Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml for details.
+ - items:
+ - const: mediatek,mt8195-disp-dsc
+
# MERGE: merge streams from two RDMA sources
- items:
- const: mediatek,mt8195-disp-merge
@@ -453,4 +457,8 @@ examples:
clocks = <&mmsys CLK_MM_DISP_OD>;
};
+ dsc0: disp_dsc_wrap@1c009000 {
+ /* See mediatek,dsc.yaml for details */
+ };
+
...
new file mode 100644
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek DSC Controller Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Jitao shi <jitao.shi@mediatek.com>
+ - Jason-JH Lin <jason-jh.lin@mediatek.com>
+
+description: |
+ The DSC standard is a specification of the algorithms used for
+ compressing and decompressing image display streams, including
+ the specification of the syntax and semantics of the compressed
+ video bit stream. DSC is designed for real-time systems with
+ real-time compression, transmission, decompression and Display.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-disp-dsc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: DSC Wrapper Clock
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ mediatek,gce-client-reg:
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, such as gce node, subsys id, offset
+ and register size. The subsys id that is mapping to the register of display
+ function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ For example, The mediatek,gce-client-reg property of OVL in mt8173 is
+ <&gce SUBSYS_1400XXXX 0xc000 0x1000>.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ dsc0: disp_dsc_wrap@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+
+...
1. Add DSC definition file for mt8195 display. 2. Add mediatek,dsc.yaml to decribe DSC module in details. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> --- .../display/mediatek/mediatek,disp.yaml | 8 ++ .../display/mediatek/mediatek,dsc.yaml | 73 +++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml