From patchwork Thu Jul 15 17:37:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 12380621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 306C4C636C7 for ; Thu, 15 Jul 2021 17:40:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 04BFA61370 for ; Thu, 15 Jul 2021 17:39:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 04BFA61370 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VyH7vHhumv1YbNd48NFiF5O7OqAyOcbPxIRDvDoQiJM=; b=jxKK0jBw12oE5l tc9lPGyPQLXCEz/lu6+i7Rg1/x74wiLetq78EF0Mq3W+vdGRgnUG5KHqPq01644Y0ZPsRx4UH8LoP wejL55JgmgZ6VvUyKi0blIGPWPzQZ3q1UT4ixKoWfk0v3Xa8rP1+XseWKxauGjsDNiTpA0oShuFL4 LpCVUsdp+AHk4kGs6nveJgtsHyjQpbJa1FzfQBnKaGzH3bPiuyZPytUqeYZIu0nZ5E8T/BoUi5mlv mKVniS4lzbuSQv9uPfrOJzeS7YstAHiRQOxo6ogZNyYeoVFu0FIAXyeu9B4TeVAB6o6+6k4AIBLOz 06Fk61FE3CCBCU8PZVxg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m45Kw-001nSr-8F; Thu, 15 Jul 2021 17:39:50 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m45JM-001mrW-8F; Thu, 15 Jul 2021 17:38:14 +0000 X-UUID: 51e66f580be24c98929d5777599277b8-20210715 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=EaEuQA1LnGuWsA80ED/Kw2eWoITwny2CEiDU9rb6Li4=; b=L8pwkCVajTXkJIRp5Ht0ub/iGNAwpc9htCMWzOGwm5OLCRVq9spGWXI8SDMXbVy9V67Nn3QvukkOp9VZPB8MHSwTtvzpRsRDNkrx6xet1xgr8XxJXry0ke9pZP1M7n2n9TnCMO9wA1XamajpW+tnwW1sg9bVSaujlHl2heOm4Gk=; X-UUID: 51e66f580be24c98929d5777599277b8-20210715 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 204915821; Thu, 15 Jul 2021 10:38:02 -0700 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 15 Jul 2021 10:38:00 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 16 Jul 2021 01:37:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 16 Jul 2021 01:37:52 +0800 From: jason-jh.lin To: , CC: , , , , , , , Subject: [PATCH v3 04/12] dt-bindings: mediatek: add DSC definition for mt8195 Date: Fri, 16 Jul 2021 01:37:42 +0800 Message-ID: <20210715173750.10852-5-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210715173750.10852-1-jason-jh.lin@mediatek.com> References: <20210715173750.10852-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210715_103812_345519_5082FF8B X-CRM114-Status: GOOD ( 16.31 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org 1. Add DSC definition file for mt8195 display. 2. Add mediatek,dsc.yaml to decribe DSC module in details. Signed-off-by: jason-jh.lin --- .../display/mediatek/mediatek,disp.yaml | 8 ++ .../display/mediatek/mediatek,dsc.yaml | 73 +++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml index 8beeb9c3c057..aac1796e3f6b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml @@ -156,6 +156,10 @@ properties: - enum: - mediatek,mt8183-disp-gamma + # DSC: see Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml for details. + - items: + - const: mediatek,mt8195-disp-dsc + # MERGE: merge streams from two RDMA sources - items: - const: mediatek,mt8195-disp-merge @@ -453,4 +457,8 @@ examples: clocks = <&mmsys CLK_MM_DISP_OD>; }; + dsc0: disp_dsc_wrap@1c009000 { + /* See mediatek,dsc.yaml for details */ + }; + ... diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml new file mode 100644 index 000000000000..f575532bfb21 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: mediatek DSC Controller Device Tree Bindings + +maintainers: + - CK Hu + - Jitao shi + - Jason-JH Lin + +description: | + The DSC standard is a specification of the algorithms used for + compressing and decompressing image display streams, including + the specification of the syntax and semantics of the compressed + video bit stream. DSC is designed for real-time systems with + real-time compression, transmission, decompression and Display. + +properties: + compatible: + oneOf: + - items: + - const: mediatek,mt8195-disp-dsc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: DSC Wrapper Clock + + power-domains: + description: A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + + mediatek,gce-client-reg: + description: The register of display function block to be set by gce. + There are 4 arguments in this property, such as gce node, subsys id, offset + and register size. The subsys id that is mapping to the register of display + function blocks is defined in the gce header + include/include/dt-bindings/gce/-gce.h of each chips. + For example, The mediatek,gce-client-reg property of OVL in mt8173 is + <&gce SUBSYS_1400XXXX 0xc000 0x1000>. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + dsc0: disp_dsc_wrap@1c009000 { + compatible = "mediatek,mt8195-disp-dsc"; + reg = <0 0x1c009000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; + mediatek,gce-client-reg = + <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>; + }; + +...