From patchwork Thu Jul 29 15:49:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12409019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3593AC4320A for ; Thu, 29 Jul 2021 15:49:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 024BD60F43 for ; Thu, 29 Jul 2021 15:49:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 024BD60F43 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vBkr9sg3vleB8Otnue6N0kUfHzT6V2kNOBzGrTS6lIE=; b=uJRjbWm1FcMsk2 riNH6Of/NcTOvFpQ9nK0tm+WsP7heAU6DXYd/YmGxjhoUxIVLp2ACYhSln8IeKx0zXIHDr7j55XW6 OWfaFLKvC3v4/K7ZpMJpfVsttIemlb5tBctUxnzn20czvyxD2qS2jQtNIginu4+gTtHZUTbvuH9Ei D/94GEugXUEzIHGBCQ89rSVB/wfhYrYOHMmcqgSNBDxJZkv20pKOD1/sOqCpSexnzuZbEDt7ALagT CQnlBB5ofYT1o9uesX1JawuC44h3PPBd16L61GY1brvEzqDVZHUK616s6urUMI/YPlThdzC0M4yy9 fiybeQRlFAFLKGK/eiVw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m98I0-004p17-R4; Thu, 29 Jul 2021 15:49:40 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m98Hp-004ouK-5e; Thu, 29 Jul 2021 15:49:34 +0000 X-UUID: f7e2cc8711fb426288d10ae613564dad-20210729 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BQL45hKKQEAlHxnZLZvPLysumbKt7ZfhHGJ+pOKM7Rw=; b=S4815G9w6D6Sm2SS/wFTFtaUrpDiZiTiR6g0Vv0nNte6ftVcvFhvGeX2vIzYg3YkwYaj6gzXzm8SjFlyg49nV2s6OMjQBezLtWcDAA40QHaWuzBu0oLB9DXFagzgi3ssrOXe8x6l6aQr+rQC1O0QM4gZWFAXQXSE7/n4Ud2oKds=; X-UUID: f7e2cc8711fb426288d10ae613564dad-20210729 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1724147960; Thu, 29 Jul 2021 08:49:24 -0700 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Jul 2021 08:49:22 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Jul 2021 23:49:14 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 29 Jul 2021 23:49:14 +0800 From: jason-jh.lin To: Rob Herring , Chun-Kuang Hu , Philipp Zabel , Enric Balletbo Serra CC: David Airlie , Daniel Vetter , Matthias Brugger , Fabien Parent , , Jitao shi , , , , , , , , Subject: [PATCH v2 4/5] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding Date: Thu, 29 Jul 2021 23:49:11 +0800 Message-ID: <20210729154912.20051-5-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210729154912.20051-1-jason-jh.lin@mediatek.com> References: <20210729154912.20051-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210729_084929_380658_89F50070 X-CRM114-Status: GOOD ( 15.16 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org 1. Add mediatek,dsc.yaml to decribe DSC module in details. 2. Add mt8195 SoC binding to mediatek,dsc.yaml. Signed-off-by: jason-jh.lin --- .../display/mediatek/mediatek,dsc.yaml | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml new file mode 100644 index 000000000000..f575532bfb21 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: mediatek DSC Controller Device Tree Bindings + +maintainers: + - CK Hu + - Jitao shi + - Jason-JH Lin + +description: | + The DSC standard is a specification of the algorithms used for + compressing and decompressing image display streams, including + the specification of the syntax and semantics of the compressed + video bit stream. DSC is designed for real-time systems with + real-time compression, transmission, decompression and Display. + +properties: + compatible: + oneOf: + - items: + - const: mediatek,mt8195-disp-dsc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: DSC Wrapper Clock + + power-domains: + description: A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + + mediatek,gce-client-reg: + description: The register of display function block to be set by gce. + There are 4 arguments in this property, such as gce node, subsys id, offset + and register size. The subsys id that is mapping to the register of display + function blocks is defined in the gce header + include/include/dt-bindings/gce/-gce.h of each chips. + For example, The mediatek,gce-client-reg property of OVL in mt8173 is + <&gce SUBSYS_1400XXXX 0xc000 0x1000>. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + dsc0: disp_dsc_wrap@1c009000 { + compatible = "mediatek,mt8195-disp-dsc"; + reg = <0 0x1c009000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; + mediatek,gce-client-reg = + <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>; + }; + +...