diff mbox series

[v6,5/7] drm/mediatek: add DSC support for mediatek-drm

Message ID 20210805205226.24880-6-jason-jh.lin@mediatek.com (mailing list archive)
State New, archived
Headers show
Series Add Mediatek Soc DRM (vdosys0) support for mt8195 | expand

Commit Message

Jason-JH Lin (林睿祥) Aug. 5, 2021, 8:52 p.m. UTC 
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-4-jason-jh.lin@mediatek.com/
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 +++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
 2 files changed, 63 insertions(+)

Comments

Chun-Kuang Hu Aug. 6, 2021, 4:44 p.m. UTC | #1 
Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> DSC is designed for real-time systems with real-time compression,
> transmission, decompression and display.
> The DSC standard is a specification of the algorithms used for
> compressing and decompressing image display streams, including
> the specification of the syntax and semantics of the compressed
> video bit stream.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
>
> [1] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-4-jason-jh.lin@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 +++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
>  2 files changed, 63 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 328ee19f931e..24c7b004fe4d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -43,6 +43,12 @@
>  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
>  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
>
> +#define DISP_REG_DSC_CON                       0x0000
> +#define DSC_EN                                 BIT(0)
> +#define DSC_DUAL_INOUT                         BIT(2)
> +#define DSC_BYPASS                             BIT(4)
> +#define DSC_UFOE_SEL                           BIT(16)
> +
>  #define DISP_REG_OD_EN                         0x0000
>  #define DISP_REG_OD_CFG                                0x0020
>  #define OD_RELAYMODE                           BIT(0)
> @@ -209,6 +215,35 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
>                               DISP_DITHERING, cmdq_pkt);
>  }
>
> +static void mtk_dsc_config(struct device *dev, unsigned int w,
> +                          unsigned int h, unsigned int vrefresh,
> +                          unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       /* dsc bypass mode */
> +       mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_DSC_CON, DSC_BYPASS);
> +       mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_DSC_CON, DSC_UFOE_SEL);
> +       mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> +}
> +
> +static void mtk_dsc_start(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
> +}
> +
> +static void mtk_dsc_stop(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
> +}
> +
>  static void mtk_od_config(struct device *dev, unsigned int w,
>                           unsigned int h, unsigned int vrefresh,
>                           unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -272,6 +307,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
>         .stop = mtk_dpi_stop,
>  };
>
> +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> +       .clk_enable = mtk_ddp_clk_enable,
> +       .clk_disable = mtk_ddp_clk_disable,
> +       .config = mtk_dsc_config,
> +       .start = mtk_dsc_start,
> +       .stop = mtk_dsc_stop,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_dsi = {
>         .start = mtk_dsi_ddp_start,
>         .stop = mtk_dsi_ddp_stop,
> @@ -286,6 +329,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
>         .stop = mtk_gamma_stop,
>  };
>
> +static const struct mtk_ddp_comp_funcs ddp_merge = {
> +       .clk_enable = mtk_merge_clk_enable,
> +       .clk_disable = mtk_merge_clk_disable,
> +       .start = mtk_merge_start,
> +       .stop = mtk_merge_stop,
> +       .config = mtk_merge_config,
> +};

Move the merge modification to the patch of merge.

> +
>  static const struct mtk_ddp_comp_funcs ddp_od = {
>         .clk_enable = mtk_ddp_clk_enable,
>         .clk_disable = mtk_ddp_clk_disable,
> @@ -333,7 +384,9 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>         [MTK_DISP_CCORR] = "ccorr",
>         [MTK_DISP_COLOR] = "color",
>         [MTK_DISP_DITHER] = "dither",
> +       [MTK_DISP_DSC] = "dsc",
>         [MTK_DISP_GAMMA] = "gamma",
> +       [MTK_DISP_MERGE] = "merge",

Ditto.

>         [MTK_DISP_MUTEX] = "mutex",
>         [MTK_DISP_OD] = "od",
>         [MTK_DISP_OVL] = "ovl",
> @@ -362,11 +415,19 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
>         [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,    0, &ddp_dither },
>         [DDP_COMPONENT_DPI0]    = { MTK_DPI,            0, &ddp_dpi },
>         [DDP_COMPONENT_DPI1]    = { MTK_DPI,            1, &ddp_dpi },
> +       [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc },
> +       [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc },
>         [DDP_COMPONENT_DSI0]    = { MTK_DSI,            0, &ddp_dsi },
>         [DDP_COMPONENT_DSI1]    = { MTK_DSI,            1, &ddp_dsi },
>         [DDP_COMPONENT_DSI2]    = { MTK_DSI,            2, &ddp_dsi },
>         [DDP_COMPONENT_DSI3]    = { MTK_DSI,            3, &ddp_dsi },
>         [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA,     0, &ddp_gamma },
> +       [DDP_COMPONENT_MERGE0]  = { MTK_DISP_MERGE,     0, &ddp_merge },
> +       [DDP_COMPONENT_MERGE1]  = { MTK_DISP_MERGE,     1, &ddp_merge },
> +       [DDP_COMPONENT_MERGE2]  = { MTK_DISP_MERGE,     2, &ddp_merge },
> +       [DDP_COMPONENT_MERGE3]  = { MTK_DISP_MERGE,     3, &ddp_merge },
> +       [DDP_COMPONENT_MERGE4]  = { MTK_DISP_MERGE,     4, &ddp_merge },
> +       [DDP_COMPONENT_MERGE5]  = { MTK_DISP_MERGE,     5, &ddp_merge },

Ditto.

>         [DDP_COMPONENT_OD0]     = { MTK_DISP_OD,        0, &ddp_od },
>         [DDP_COMPONENT_OD1]     = { MTK_DISP_OD,        1, &ddp_od },
>         [DDP_COMPONENT_OVL0]    = { MTK_DISP_OVL,       0, &ddp_ovl },
> @@ -497,6 +558,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>             type == MTK_DISP_CCORR ||
>             type == MTK_DISP_COLOR ||
>             type == MTK_DISP_GAMMA ||
> +           type == MTK_DISP_MERGE ||

Ditto.

Regards,
Chun-Kuang.

>             type == MTK_DISP_OVL ||
>             type == MTK_DISP_OVL_2L ||
>             type == MTK_DISP_PWM ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index d317b944df66..560be6bc9d0e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
>         MTK_DISP_CCORR,
>         MTK_DISP_COLOR,
>         MTK_DISP_DITHER,
> +       MTK_DISP_DSC,
>         MTK_DISP_GAMMA,
>         MTK_DISP_MUTEX,
>         MTK_DISP_OD,
> --
> 2.18.0
>
Jason-JH Lin (林睿祥) Aug. 11, 2021, 4:16 p.m. UTC | #2 
Hi CK,

On Sat, 2021-08-07 at 00:44 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
> > 
> > DSC is designed for real-time systems with real-time compression,
> > transmission, decompression and display.
> > The DSC standard is a specification of the algorithms used for
> > compressing and decompressing image display streams, including
> > the specification of the syntax and semantics of the compressed
> > video bit stream.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > This patch is base on [1]
> > 
> > [1] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC
> > binding
> > 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-4-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!z1RWCIbQoMLarG_-uxUAQS__rpGyCB2Xk7IFVb_Vbo-RoXrWDE4cLvcERABbW11zbL1o$
> >  
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62
> > +++++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
> >  2 files changed, 63 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 328ee19f931e..24c7b004fe4d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -43,6 +43,12 @@
> >  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
> >  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
> > 
> > +#define DISP_REG_DSC_CON                       0x0000
> > +#define DSC_EN                                 BIT(0)
> > +#define DSC_DUAL_INOUT                         BIT(2)
> > +#define DSC_BYPASS                             BIT(4)
> > +#define DSC_UFOE_SEL                           BIT(16)
> > +
> >  #define DISP_REG_OD_EN                         0x0000
> >  #define DISP_REG_OD_CFG                                0x0020
> >  #define OD_RELAYMODE                           BIT(0)
> > @@ -209,6 +215,35 @@ static void mtk_dither_set(struct device *dev,
> > unsigned int bpc,
> >                               DISP_DITHERING, cmdq_pkt);
> >  }
> > 
> > +static void mtk_dsc_config(struct device *dev, unsigned int w,
> > +                          unsigned int h, unsigned int vrefresh,
> > +                          unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       /* dsc bypass mode */
> > +       mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg,
> > priv->regs,
> > +                          DISP_REG_DSC_CON, DSC_BYPASS);
> > +       mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, 
> > priv->regs,
> > +                          DISP_REG_DSC_CON, DSC_UFOE_SEL);
> > +       mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv-
> > >cmdq_reg, priv->regs,
> > +                          DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> > +}
> > +
> > +static void mtk_dsc_start(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
> > +}
> > +
> > +static void mtk_dsc_stop(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
> > +}
> > +
> >  static void mtk_od_config(struct device *dev, unsigned int w,
> >                           unsigned int h, unsigned int vrefresh,
> >                           unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > @@ -272,6 +307,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi
> > = {
> >         .stop = mtk_dpi_stop,
> >  };
> > 
> > +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> > +       .clk_enable = mtk_ddp_clk_enable,
> > +       .clk_disable = mtk_ddp_clk_disable,
> > +       .config = mtk_dsc_config,
> > +       .start = mtk_dsc_start,
> > +       .stop = mtk_dsc_stop,
> > +};
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_dsi = {
> >         .start = mtk_dsi_ddp_start,
> >         .stop = mtk_dsi_ddp_stop,
> > @@ -286,6 +329,14 @@ static const struct mtk_ddp_comp_funcs
> > ddp_gamma = {
> >         .stop = mtk_gamma_stop,
> >  };
> > 
> > +static const struct mtk_ddp_comp_funcs ddp_merge = {
> > +       .clk_enable = mtk_merge_clk_enable,
> > +       .clk_disable = mtk_merge_clk_disable,
> > +       .start = mtk_merge_start,
> > +       .stop = mtk_merge_stop,
> > +       .config = mtk_merge_config,
> > +};
> 
> Move the merge modification to the patch of merge.
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_od = {
> >         .clk_enable = mtk_ddp_clk_enable,
> >         .clk_disable = mtk_ddp_clk_disable,
> > @@ -333,7 +384,9 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> >         [MTK_DISP_CCORR] = "ccorr",
> >         [MTK_DISP_COLOR] = "color",
> >         [MTK_DISP_DITHER] = "dither",
> > +       [MTK_DISP_DSC] = "dsc",
> >         [MTK_DISP_GAMMA] = "gamma",
> > +       [MTK_DISP_MERGE] = "merge",
> 
> Ditto.
> 
> >         [MTK_DISP_MUTEX] = "mutex",
> >         [MTK_DISP_OD] = "od",
> >         [MTK_DISP_OVL] = "ovl",
> > @@ -362,11 +415,19 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> >         [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,    0,
> > &ddp_dither },
> >         [DDP_COMPONENT_DPI0]    = { MTK_DPI,            0, &ddp_dpi
> > },
> >         [DDP_COMPONENT_DPI1]    = { MTK_DPI,            1, &ddp_dpi
> > },
> > +       [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc
> > },
> > +       [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc
> > },
> >         [DDP_COMPONENT_DSI0]    = { MTK_DSI,            0, &ddp_dsi
> > },
> >         [DDP_COMPONENT_DSI1]    = { MTK_DSI,            1, &ddp_dsi
> > },
> >         [DDP_COMPONENT_DSI2]    = { MTK_DSI,            2, &ddp_dsi
> > },
> >         [DDP_COMPONENT_DSI3]    = { MTK_DSI,            3, &ddp_dsi
> > },
> >         [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA,     0,
> > &ddp_gamma },
> > +       [DDP_COMPONENT_MERGE0]  = { MTK_DISP_MERGE,     0,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE1]  = { MTK_DISP_MERGE,     1,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE2]  = { MTK_DISP_MERGE,     2,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE3]  = { MTK_DISP_MERGE,     3,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE4]  = { MTK_DISP_MERGE,     4,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE5]  = { MTK_DISP_MERGE,     5,
> > &ddp_merge },
> 
> Ditto.
> 
> >         [DDP_COMPONENT_OD0]     = { MTK_DISP_OD,        0, &ddp_od
> > },
> >         [DDP_COMPONENT_OD1]     = { MTK_DISP_OD,        1, &ddp_od
> > },
> >         [DDP_COMPONENT_OVL0]    = { MTK_DISP_OVL,       0, &ddp_ovl
> > },
> > @@ -497,6 +558,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> > struct mtk_ddp_comp *comp,
> >             type == MTK_DISP_CCORR ||
> >             type == MTK_DISP_COLOR ||
> >             type == MTK_DISP_GAMMA ||
> > +           type == MTK_DISP_MERGE ||
> 
> Ditto.
> 
> Regards,
> Chun-Kuang.
> 

OK, I'll move them into MERGE patch.

Regards,
Jason-JH.Lin
> >             type == MTK_DISP_OVL ||
> >             type == MTK_DISP_OVL_2L ||
> >             type == MTK_DISP_PWM ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index d317b944df66..560be6bc9d0e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
> >         MTK_DISP_CCORR,
> >         MTK_DISP_COLOR,
> >         MTK_DISP_DITHER,
> > +       MTK_DISP_DSC,
> >         MTK_DISP_GAMMA,
> >         MTK_DISP_MUTEX,
> >         MTK_DISP_OD,
> > --
> > 2.18.0
> >
diff mbox series

Patch

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 328ee19f931e..24c7b004fe4d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -43,6 +43,12 @@ 
 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
 
+#define DISP_REG_DSC_CON			0x0000
+#define DSC_EN					BIT(0)
+#define DSC_DUAL_INOUT				BIT(2)
+#define DSC_BYPASS				BIT(4)
+#define DSC_UFOE_SEL				BIT(16)
+
 #define DISP_REG_OD_EN				0x0000
 #define DISP_REG_OD_CFG				0x0020
 #define OD_RELAYMODE				BIT(0)
@@ -209,6 +215,35 @@  static void mtk_dither_set(struct device *dev, unsigned int bpc,
 			      DISP_DITHERING, cmdq_pkt);
 }
 
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+			   unsigned int h, unsigned int vrefresh,
+			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* dsc bypass mode */
+	mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_BYPASS);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_UFOE_SEL);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
 static void mtk_od_config(struct device *dev, unsigned int w,
 			  unsigned int h, unsigned int vrefresh,
 			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -272,6 +307,14 @@  static const struct mtk_ddp_comp_funcs ddp_dpi = {
 	.stop = mtk_dpi_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+	.clk_enable = mtk_ddp_clk_enable,
+	.clk_disable = mtk_ddp_clk_disable,
+	.config = mtk_dsc_config,
+	.start = mtk_dsc_start,
+	.stop = mtk_dsc_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_dsi = {
 	.start = mtk_dsi_ddp_start,
 	.stop = mtk_dsi_ddp_stop,
@@ -286,6 +329,14 @@  static const struct mtk_ddp_comp_funcs ddp_gamma = {
 	.stop = mtk_gamma_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+	.clk_enable = mtk_merge_clk_enable,
+	.clk_disable = mtk_merge_clk_disable,
+	.start = mtk_merge_start,
+	.stop = mtk_merge_stop,
+	.config = mtk_merge_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_od = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -333,7 +384,9 @@  static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_CCORR] = "ccorr",
 	[MTK_DISP_COLOR] = "color",
 	[MTK_DISP_DITHER] = "dither",
+	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MERGE] = "merge",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_OVL] = "ovl",
@@ -362,11 +415,19 @@  static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DITHER]	= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]	= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]	= { MTK_DPI,		1, &ddp_dpi },
+	[DDP_COMPONENT_DSC0]	= { MTK_DISP_DSC,	0, &ddp_dsc },
+	[DDP_COMPONENT_DSC1]	= { MTK_DISP_DSC,	1, &ddp_dsc },
 	[DDP_COMPONENT_DSI0]	= { MTK_DSI,		0, &ddp_dsi },
 	[DDP_COMPONENT_DSI1]	= { MTK_DSI,		1, &ddp_dsi },
 	[DDP_COMPONENT_DSI2]	= { MTK_DSI,		2, &ddp_dsi },
 	[DDP_COMPONENT_DSI3]	= { MTK_DSI,		3, &ddp_dsi },
 	[DDP_COMPONENT_GAMMA]	= { MTK_DISP_GAMMA,	0, &ddp_gamma },
+	[DDP_COMPONENT_MERGE0]	= { MTK_DISP_MERGE,	0, &ddp_merge },
+	[DDP_COMPONENT_MERGE1]	= { MTK_DISP_MERGE,	1, &ddp_merge },
+	[DDP_COMPONENT_MERGE2]	= { MTK_DISP_MERGE,	2, &ddp_merge },
+	[DDP_COMPONENT_MERGE3]	= { MTK_DISP_MERGE,	3, &ddp_merge },
+	[DDP_COMPONENT_MERGE4]	= { MTK_DISP_MERGE,	4, &ddp_merge },
+	[DDP_COMPONENT_MERGE5]	= { MTK_DISP_MERGE,	5, &ddp_merge },
 	[DDP_COMPONENT_OD0]	= { MTK_DISP_OD,	0, &ddp_od },
 	[DDP_COMPONENT_OD1]	= { MTK_DISP_OD,	1, &ddp_od },
 	[DDP_COMPONENT_OVL0]	= { MTK_DISP_OVL,	0, &ddp_ovl },
@@ -497,6 +558,7 @@  int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
+	    type == MTK_DISP_MERGE ||
 	    type == MTK_DISP_OVL ||
 	    type == MTK_DISP_OVL_2L ||
 	    type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index d317b944df66..560be6bc9d0e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@  enum mtk_ddp_comp_type {
 	MTK_DISP_CCORR,
 	MTK_DISP_COLOR,
 	MTK_DISP_DITHER,
+	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,