| Message ID | 20210819022327.13040-4-jason-jh.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Mediatek Soc DRM (vdosys0) support for mt8195 | expand |
Hi, Jason: jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:23寫道： > > 1. Add mediatek,dsc.yaml to describe DSC module in details. > 2. Add mt8195 SoC binding to mediatek,dsc.yaml. > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > --- > .../display/mediatek/mediatek,dsc.yaml | 69 +++++++++++++++++++ > 1 file changed, 69 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml > new file mode 100644 > index 000000000000..f94a95c6a1c5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml > @@ -0,0 +1,69 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: mediatek display DSC controller > + > +maintainers: > + - CK Hu <ck.hu@mediatek.com> According to [1], the maintainer should be Chun-Kuang Hu <chunkuang.hu@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de> [1] https://www.kernel.org/doc/html/latest/process/maintainers.html > + > +description: | > + The DSC standard is a specification of the algorithms used for > + compressing and decompressing image display streams, including > + the specification of the syntax and semantics of the compressed > + video bit stream. DSC is designed for real-time systems with > + real-time compression, transmission, decompression and Display. > + > +properties: > + compatible: > + oneOf: > + - items: > + - const: mediatek,mt8195-disp-dsc > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: DSC Wrapper Clock > + > + power-domains: > + description: A phandle and PM domain specifier as defined by bindings of > + the power controller specified by phandle. See > + Documentation/devicetree/bindings/power/power-domain.yaml for details. > + > + mediatek,gce-client-reg: > + description: > + The register of display function block to be set by gce. There are 4 arguments, > + such as gce node, subsys id, offset and register size. The subsys id that is > + mapping to the register of display function blocks is defined in the gce header > + include/include/dt-bindings/gce/<chip>-gce.h of each chips. > + $ref: /schemas/types.yaml#/definitions/phandle-array > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - power-domains > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + > + dsc0: disp_dsc_wrap@1c009000 { > + compatible = "mediatek,mt8195-disp-dsc"; > + reg = <0 0x1c009000 0 0x1000>; > + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>; > + }; > + > -- > 2.18.0 >
Hi Chun-Kuang, Thanks for the review. On Sun, 2021-08-22 at 07:14 +0800, Chun-Kuang Hu wrote: > Hi, Jason: > > jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:23寫道： > > > > 1. Add mediatek,dsc.yaml to describe DSC module in details. > > 2. Add mt8195 SoC binding to mediatek,dsc.yaml. > > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > > --- > > .../display/mediatek/mediatek,dsc.yaml | 69 > > +++++++++++++++++++ > > 1 file changed, 69 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yam > > l > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.y > > aml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.y > > aml > > new file mode 100644 > > index 000000000000..f94a95c6a1c5 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.y > > aml > > @@ -0,0 +1,69 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml*__;Iw!!CTRNKA9wMg0ARbw!2qwvJnFTgJzfk1n0OVXqGlPjYco2bBUZtWFzb4n8gzHXyFFJZ7MT4QWO4RDznHmSWyiO$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2qwvJnFTgJzfk1n0OVXqGlPjYco2bBUZtWFzb4n8gzHXyFFJZ7MT4QWO4RDznNC1w7FX$ > > > > + > > +title: mediatek display DSC controller > > + > > +maintainers: > > + - CK Hu <ck.hu@mediatek.com> > > According to [1], the maintainer should be > > Chun-Kuang Hu <chunkuang.hu@kernel.org>, Philipp Zabel < > p.zabel@pengutronix.de> > > [1] > https://urldefense.com/v3/__https://www.kernel.org/doc/html/latest/process/maintainers.html__;!!CTRNKA9wMg0ARbw!2qwvJnFTgJzfk1n0OVXqGlPjYco2bBUZtWFzb4n8gzHXyFFJZ7MT4QWO4RDznMdx7tAe$ > OK, I'll fix it and also the [PATCH v8 02/13] in this series. Regards, Jason-JH.Lin > > > + > > +description: | > > + The DSC standard is a specification of the algorithms used for > > + compressing and decompressing image display streams, including > > + the specification of the syntax and semantics of the compressed > > + video bit stream. DSC is designed for real-time systems with > > + real-time compression, transmission, decompression and Display. > > + > > +properties: > > + compatible: > > + oneOf: > > + - items: > > + - const: mediatek,mt8195-disp-dsc > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: DSC Wrapper Clock > > + > > + power-domains: > > + description: A phandle and PM domain specifier as defined by > > bindings of > > + the power controller specified by phandle. See > > + Documentation/devicetree/bindings/power/power-domain.yaml > > for details. > > + > > + mediatek,gce-client-reg: > > + description: > > + The register of display function block to be set by gce. > > There are 4 arguments, > > + such as gce node, subsys id, offset and register size. The > > subsys id that is > > + mapping to the register of display function blocks is > > defined in the gce header > > + include/include/dt-bindings/gce/<chip>-gce.h of each > > chips. > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - power-domains > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + > > + dsc0: disp_dsc_wrap@1c009000 { > > + compatible = "mediatek,mt8195-disp-dsc"; > > + reg = <0 0x1c009000 0 0x1000>; > > + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > > + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; > > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 > > 0x1000>; > > + }; > > + > > -- > > 2.18.0 > >
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml new file mode 100644 index 000000000000..f94a95c6a1c5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: mediatek display DSC controller + +maintainers: + - CK Hu <ck.hu@mediatek.com> + +description: | + The DSC standard is a specification of the algorithms used for + compressing and decompressing image display streams, including + the specification of the syntax and semantics of the compressed + video bit stream. DSC is designed for real-time systems with + real-time compression, transmission, decompression and Display. + +properties: + compatible: + oneOf: + - items: + - const: mediatek,mt8195-disp-dsc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: DSC Wrapper Clock + + power-domains: + description: A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - power-domains + - clocks + +additionalProperties: false + +examples: + - | + + dsc0: disp_dsc_wrap@1c009000 { + compatible = "mediatek,mt8195-disp-dsc"; + reg = <0 0x1c009000 0 0x1000>; + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>; + }; +
1. Add mediatek,dsc.yaml to describe DSC module in details. 2. Add mt8195 SoC binding to mediatek,dsc.yaml. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> --- .../display/mediatek/mediatek,dsc.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml