| Message ID | 20210820111504.350-12-chun-jie.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Mediatek MT8195 clock support | expand |
On Fri, Aug 20, 2021 at 7:23 PM Chun-Jie Chen <chun-jie.chen@mediatek.com> wrote: > > Add MT8195 ccusys clock controller which provides clock gate > control in Camera Computing Unit. Could you offer a bit more explanation about this unit? Is it an ISP? Or some other function that does computation on images? > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > --- > drivers/clk/mediatek/Makefile | 3 +- > drivers/clk/mediatek/clk-mt8195-ccu.c | 50 +++++++++++++++++++++++++++ > 2 files changed, 52 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/mediatek/clk-mt8195-ccu.c > > diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile > index 718bbb04191b..03fb020834f3 100644 > --- a/drivers/clk/mediatek/Makefile > +++ b/drivers/clk/mediatek/Makefile > @@ -80,6 +80,7 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o > obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o > obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o > obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o > -obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o clk-mt8195-cam.o > +obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o clk-mt8195-cam.o \ > + clk-mt8195-ccu.o When wrapping, please align with previous line. "clk-mt8195-ccu.o" should align with "clk-mt8195-apmixedsys.o". ChenYu
On Mon, 2021-08-23 at 20:13 +0800, Chen-Yu Tsai wrote: > On Fri, Aug 20, 2021 at 7:23 PM Chun-Jie Chen > <chun-jie.chen@mediatek.com> wrote: > > > > Add MT8195 ccusys clock controller which provides clock gate > > control in Camera Computing Unit. > > Could you offer a bit more explanation about this unit? Is it an ISP? > Or some other function that does computation on images? > CCU could access ISP HW control register and could be used for ISP pipeline control. The use case is like secure camera or doing post- processing on ISP statistic data. Thanks! Best Regards, Chun-Jie > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > > --- > > drivers/clk/mediatek/Makefile | 3 +- > > drivers/clk/mediatek/clk-mt8195-ccu.c | 50 > > +++++++++++++++++++++++++++ > > 2 files changed, 52 insertions(+), 1 deletion(-) > > create mode 100644 drivers/clk/mediatek/clk-mt8195-ccu.c > > > > diff --git a/drivers/clk/mediatek/Makefile > > b/drivers/clk/mediatek/Makefile > > index 718bbb04191b..03fb020834f3 100644 > > --- a/drivers/clk/mediatek/Makefile > > +++ b/drivers/clk/mediatek/Makefile > > @@ -80,6 +80,7 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk- > > mt8192-msdc.o > > obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o > > obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o > > obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o > > -obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk- > > mt8195-topckgen.o clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o clk- > > mt8195-cam.o > > +obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk- > > mt8195-topckgen.o clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o clk- > > mt8195-cam.o \ > > + clk-mt8195-ccu.o > > When wrapping, please align with previous line. "clk-mt8195-ccu.o" > should > align with "clk-mt8195-apmixedsys.o". > > > ChenYu
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 718bbb04191b..03fb020834f3 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -80,6 +80,7 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o -obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o clk-mt8195-cam.o +obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o clk-mt8195-cam.o \ + clk-mt8195-ccu.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8195-ccu.c b/drivers/clk/mediatek/clk-mt8195-ccu.c new file mode 100644 index 000000000000..d883091e0085 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8195-ccu.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (c) 2021 MediaTek Inc. +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include <dt-bindings/clock/mt8195-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +static const struct mtk_gate_regs ccu_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_CCU(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate ccu_clks[] = { + GATE_CCU(CLK_CCU_LARB18, "ccu_larb18", "top_ccu", 0), + GATE_CCU(CLK_CCU_AHB, "ccu_ahb", "top_ccu", 1), + GATE_CCU(CLK_CCU_CCU0, "ccu_ccu0", "top_ccu", 2), + GATE_CCU(CLK_CCU_CCU1, "ccu_ccu1", "top_ccu", 3), +}; + +static const struct mtk_clk_desc ccu_desc = { + .clks = ccu_clks, + .num_clks = ARRAY_SIZE(ccu_clks), +}; + +static const struct of_device_id of_match_clk_mt8195_ccu[] = { + { + .compatible = "mediatek,mt8195-ccusys", + .data = &ccu_desc, + }, { + /* sentinel */ + } +}; + +static struct platform_driver clk_mt8195_ccu_drv = { + .probe = mtk_clk_simple_probe, + .driver = { + .name = "clk-mt8195-ccu", + .of_match_table = of_match_clk_mt8195_ccu, + }, +}; +builtin_platform_driver(clk_mt8195_ccu_drv);