diff mbox series

[v5,04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit

Message ID 20210906071539.12953-5-nancy.lin@mediatek.com (mailing list archive)
State New, archived
Headers show
Series Add MediaTek SoC DRM (vdosys1) support for mt8195 | expand

Commit Message

Nancy Lin (林欣螢) Sept. 6, 2021, 7:15 a.m. UTC
Add vdosys1 reset control bit for MT8195 platform.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
 include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Chun-Kuang Hu Sept. 7, 2021, 4:06 p.m. UTC | #1
Hi, Nancy:

Nancy.Lin <nancy.lin@mediatek.com> 於 2021年9月6日 週一 下午3:15寫道:
>
> Add vdosys1 reset control bit for MT8195 platform.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
>  include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> index a26bccc8b957..eaaa882c09bd 100644
> --- a/include/dt-bindings/reset/mt8195-resets.h
> +++ b/include/dt-bindings/reset/mt8195-resets.h
> @@ -26,4 +26,16 @@
>
>  #define MT8195_TOPRGU_SW_RST_NUM               16
>
> +/* VDOSYS1 */
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55

Maybe you should align the indent style with TOPRGU.

Regards,
Chun-Kuang.

> +
>  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
> --
> 2.18.0
>
Nancy Lin (林欣螢) Sept. 16, 2021, 3:05 a.m. UTC | #2
Hi Chun-Kuang,

Thanks for the review.

On Wed, 2021-09-08 at 00:06 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
> 
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年9月6日 週一 下午3:15寫道:
> > 
> > Add vdosys1 reset control bit for MT8195 platform.
> > 
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> >  include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> > 
> > diff --git a/include/dt-bindings/reset/mt8195-resets.h
> > b/include/dt-bindings/reset/mt8195-resets.h
> > index a26bccc8b957..eaaa882c09bd 100644
> > --- a/include/dt-bindings/reset/mt8195-resets.h
> > +++ b/include/dt-bindings/reset/mt8195-resets.h
> > @@ -26,4 +26,16 @@
> > 
> >  #define MT8195_TOPRGU_SW_RST_NUM               16
> > 
> > +/* VDOSYS1 */
> > +#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
> > +#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
> > +#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
> > +#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
> > +#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
> > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
> > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
> > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
> > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
> > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
> 
> Maybe you should align the indent style with TOPRGU.
> 
> Regards,
> Chun-Kuang.
> 
OK, I will modify it in the next revision.

Regards,
Nancy Lin

> > +
> >  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
> > --
> > 2.18.0
> >
diff mbox series

Patch

diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..eaaa882c09bd 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,16 @@ 
 
 #define MT8195_TOPRGU_SW_RST_NUM               16
 
+/* VDOSYS1 */
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */