diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 0c97a5f016c1..8f843275ba34 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -111,4 +111,720 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 	}
 };
 
+/* VPPSYS0 MOUT */
+#define MT8195_VPPSYS0_STITCH_MOUT_EN 0xF38
+	#define MT8195_VPPSYS0_STITCH_MOUT_TO_PQ_SEL_IN BIT(0)
+	#define MT8195_VPPSYS0_STITCH_MOUT_TO_VPP1_SEL_IN BIT(1)
+#define MT8195_VPPSYS0_WARP0_MOUT_EN 0xF3C
+	#define MT8195_VPPSYS0_WARP0_MOUT_TO_PQ_SEL_IN BIT(0)
+	#define MT8195_VPPSYS0_WARP0_MOUT_TO_VPP1_SEL_IN BIT(1)
+#define MT8195_VPPSYS0_WARP1_MOUT_EN 0xF40
+	#define MT8195_VPPSYS0_WARP1_MOUT_TO_PQ_SEL_IN BIT(0)
+	#define MT8195_VPPSYS0_WARP1_MOUT_TO_VPP1_SEL_IN BIT(1)
+#define MT8195_VPPSYS0_FG_MOUT_EN 0xF44
+	#define MT8195_VPPSYS0_FG_MOUT_TO_PQ_SEL_IN BIT(0)
+	#define MT8195_VPPSYS0_FG_MOUT_TO_VPP1_SEL_IN BIT(1)
+
+/* VPPSYS1 MOUT */
+#define MT8195_SVPP2_SRC_SEL_MOUT_EN 0xF50
+	#define MT8195_SVPP2_MDP_HDR BIT(0)
+	#define MT8195_SVPP1_HDR_SRC_SEL BIT(1)
+#define MT8195_SVPP3_SRC_SEL_MOUT_EN 0xF7C
+	#define MT8195_SVPP3_MDP_HDR BIT(0)
+	#define MT8195_VPP0_DL1_SRC_SEL BIT(1)
+#define MT8195_SVPP2_MDP_HDR_MOUT_EN 0xF4C
+	#define MT8195_SVPP2_MDP_AAL BIT(0)
+	#define MT8195_SVPP1_MDP_AAL_SEL BIT(1)
+#define MT8195_SVPP3_MDP_HDR_MOUT_EN 0xF78
+	#define MT8195_SVPP3_MDP_AAL BIT(0)
+
+/* VPPSYS0 SEL_IN */
+#define MT8195_VPPSYS0_PQ_SEL_IN 0xF04
+	#define MT8195_VPPSYS0_PQ_SEL_IN_FROM_STITCH 0
+	#define MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP0 1
+	#define MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP1 2
+	#define MT8195_VPPSYS0_PQ_SEL_IN_FROM_MDP_FG 3
+#define MT8195_VPPSYS0_VPP1_SEL_IN 0xF08
+	#define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_PADDING_SOUT 0
+	#define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_STITCH 1
+	#define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP0 2
+	#define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP1 3
+	#define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_MDP_FG 4
+#define MT8195_VPPSYS0_HDR_SEL_IN 0xF0C
+	#define MT8195_VPPSYS0_HDR_SEL_IN_FROM_PQ_SOUT 0
+	#define MT8195_VPPSYS0_HDR_SEL_IN_FROM_TCC_SOUT 1
+	#define MT8195_VPPSYS0_HDR_SEL_IN_FROM_VPP1_IN_SOUT 2
+#define MT8195_VPPSYS0_AAL_SEL_IN 0xF18
+	#define MT8195_VPPSYS0_AAL_SEL_IN_FROM_MDP_HDR 0
+	#define MT8195_VPPSYS0_AAL_SEL_IN_FROM_VPP1_IN_SOUT 1
+#define MT8195_VPPSYS0_TCC_SEL_IN 0xF10
+	#define MT8195_VPPSYS0_TCC_SEL_IN_FROM_PADDING_SOUT 0
+	#define MT8195_VPPSYS0_TCC_SEL_IN_FROM_PQ_SOUT 1
+#define MT8195_VPPSYS0_WROT_SEL_IN 0xF14
+	#define MT8195_VPPSYS0_WROT_SEL_IN_FROM_TCC_SOUT 0
+	#define MT8195_VPPSYS0_WROT_SEL_IN_FROM_PADDING_SOUT 1
+	#define MT8195_VPPSYS0_WROT_SEL_IN_FROM_MDP_RDMA 2
+
+/* VPPSYS1 SEL_IN */
+#define MT8195_SVPP1_SRC_SEL_IN 0xF1C
+	#define MT8195_SVPP1_SRC_SEL_IN_FROM_SVPP1_MDP_FG 0
+	#define MT8195_SVPP1_SRC_SEL_IN_FROM_VPP0_SRC_SOUT 1
+#define MT8195_SVPP2_SRC_SEL_IN 0xF38
+	#define MT8195_SVPP2_SRC_SEL_IN_FROM_SVPP2_MDP_FG 0
+	#define MT8195_SVPP2_SRC_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT 1
+#define MT8195_SVPP3_SRC_SEL_IN 0xF64
+	#define MT8195_SVPP3_SRC_SEL_IN_FROM_SVPP3_MDP_FG 0
+	#define MT8195_SVPP3_SRC_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT 1
+#define MT8195_SVPP1_HDR_SRC_SEL_IN 0xF24
+	#define MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT 0
+	#define MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT 1
+	#define MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP2_SRC_SEL_MOUT 2
+#define MT8195_SVPP1_MDP_AAL_SEL_IN 0xF54
+	#define MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP1_MDP_HDR 0
+	#define MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP2_MDP_HDR_MOUT 1
+#define MT8195_SVPP1_TCC_SEL_IN 0xF30
+	#define MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_PATH_SOUT 0
+	#define MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT 1
+#define MT8195_VPP0_DL1_SRC_SEL_IN 0xF80
+	#define MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_SRC_SEL_MOUT 0
+	#define MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_MDP_HDR_MOUT 1
+	#define MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT 2
+#define MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN 0xF44
+	#define MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_SVPP2_MDP_AAL 0
+	#define MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT 1
+#define MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN 0xF70
+	#define MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_SVPP3_MDP_AAL 0
+	#define MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT 1
+#define MT8195_SVPP1_WROT_SRC_SEL_IN 0xF2c
+	#define MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT 0
+	#define MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT 1
+	#define MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_MDP_RDMA_SOUT 2
+#define MT8195_SVPP2_WROT_SRC_SEL_IN 0xF40
+	#define MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT 0
+	#define MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_VPP_PAD 1
+	#define MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_MDP_RDMA_SOUT 2
+#define MT8195_SVPP3_WROT_SRC_SEL_IN 0xF6c
+	#define MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_VPP0_SRC_SOUT 0
+	#define MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_VPP_PAD 1
+	#define MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_MDP_RDMA_SOUT 2
+
+/* VPPSYS0 SEL_OUT */
+#define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN 0xF20
+	#define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH 0
+	#define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP0_MOUT 1
+#define MT8195_VPPSYS0_WARP1_SOUT_SEL_IN 0xF24
+	#define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH 0
+	#define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP1_MOUT 1
+#define MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN 0xF1C
+	#define MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_FG 0
+	#define MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_WROT_SEL_IN 1
+#define MT8195_VPPSYS0_PQ_SOUT_SEL_IN 0xF28
+	#define MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_PQ_SEL_IN 0
+	#define MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_TCC_SEL_IN 1
+#define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN 0xF34
+	#define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_HDR_SEL_IN 0
+	#define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_AAL_SEL_IN 1
+	#define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_MDP_RSZ 2
+#define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN 0xF2C
+	#define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_TCC_SEL_IN 0
+	#define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_WROT_SEL_IN 1
+	#define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_VPP1_SEL_IN 2
+#define MT8195_VPPSYS0_TCC_SOUT_SEL_IN 0xF30
+	#define MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_WROT_SEL_IN 0
+	#define MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_HDR_SEL_IN 1
+
+/* VPPSYS1 SEL_OUT */
+#define MT8195_SVPP1_MDP_RDMA_SOUT_SEL 0xF18
+	#define MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_MDP_FG 0
+	#define MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_RSZ 1
+	#define MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL 2
+#define MT8195_SVPP2_MDP_RDMA_SOUT_SEL 0xF90
+	#define MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_FG 0
+	#define MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL 1
+#define MT8195_SVPP3_MDP_RDMA_SOUT_SEL 0xF60
+	#define MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_MDP_FG 0
+	#define MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL 1
+#define MT8195_VPP0_SRC_SOUT_SEL 0xF8C
+	#define MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP1_SRC_SEL 0
+	#define MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_MDP_RSZ 1
+	#define MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL 2
+#define MT8195_SVPP1_SRC_SEL_SOUT_SEL 0xF20
+	#define MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL 0
+	#define MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_TCC_SEL 1
+	#define MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_VPP0_DL1_SRC_SEL 2
+#define MT8195_SVPP2_COLOR_SOUT_SEL 0xF3c
+	#define MT8195_SVPP2_COLOR_SOUT_SEL_TO_SVPP2_VPP_PAD 0
+	#define MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO0_DL0_RELAY 1
+	#define MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO1_DL0_RELAY 2
+#define MT8195_SVPP3_COLOR_SOUT_SEL 0xF68
+	#define MT8195_SVPP3_COLOR_SOUT_SEL_TO_SVPP3_VPP_PAD 0
+	#define MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO0_DL1_RELAY 1
+	#define MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO1_DL1_RELAY 2
+#define MT8195_SVPP1_TCC_SOUT_SEL 0xF34
+	#define MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL 0
+	#define MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL 1
+#define MT8195_SVPP1_PATH_SOUT_SEL 0xF28
+	#define MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_TCC_SEL 0
+	#define MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL 1
+	#define MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL 2
+
+/* VPPSYS0 */
+#define VPPSYS0_HW_DCM_1ST_DIS0 0x050
+
+/* VPPSYS1 */
+#define VPPSYS1_HW_DCM_1ST_DIS0 0x150
+#define VPPSYS1_HW_DCM_1ST_DIS1 0x160
+#define VPPSYS1_HW_DCM_2ND_DIS0 0x1a0
+#define VPPSYS1_HW_DCM_2ND_DIS1 0x1b0
+#define VPP0_DL_IRELAY_WR 0x920
+#define SVPP2_BUF_BF_RSZ_SWITCH 0xf48
+#define SVPP3_BUF_BF_RSZ_SWITCH 0xf74
+
+static const u32 mmsys_mt8195_mdp_vppsys_config_table[] = {
+	VPPSYS0_HW_DCM_1ST_DIS0,
+	VPP0_DL_IRELAY_WR,
+	VPPSYS1_HW_DCM_1ST_DIS0,
+	VPPSYS1_HW_DCM_1ST_DIS1,
+	VPPSYS1_HW_DCM_2ND_DIS0,
+	VPPSYS1_HW_DCM_2ND_DIS1,
+	SVPP2_BUF_BF_RSZ_SWITCH,
+	SVPP3_BUF_BF_RSZ_SWITCH,
+};
+
+static const struct mtk_mmsys_routes mmsys_mt8195_mdp_routing_table[] = {
+	/* VPPSYS0 MOUT */
+	{
+		MDP_COMP_STITCH, MDP_COMP_PQ0_SOUT,
+		MT8195_VPPSYS0_STITCH_MOUT_EN,
+		MT8195_VPPSYS0_STITCH_MOUT_TO_PQ_SEL_IN,
+		MT8195_VPPSYS0_STITCH_MOUT_TO_PQ_SEL_IN
+	}, {
+		MDP_COMP_STITCH, MDP_COMP_VPP0_SOUT,
+		MT8195_VPPSYS0_STITCH_MOUT_EN,
+		MT8195_VPPSYS0_STITCH_MOUT_TO_VPP1_SEL_IN,
+		MT8195_VPPSYS0_STITCH_MOUT_TO_VPP1_SEL_IN
+	}, {
+		MDP_COMP_CAMIN, MDP_COMP_PQ0_SOUT,
+		MT8195_VPPSYS0_WARP0_MOUT_EN,
+		MT8195_VPPSYS0_WARP0_MOUT_TO_PQ_SEL_IN,
+		MT8195_VPPSYS0_WARP0_MOUT_TO_PQ_SEL_IN
+	}, {
+		MDP_COMP_CAMIN, MDP_COMP_VPP0_SOUT,
+		MT8195_VPPSYS0_WARP0_MOUT_EN,
+		MT8195_VPPSYS0_WARP0_MOUT_TO_VPP1_SEL_IN,
+		MT8195_VPPSYS0_WARP0_MOUT_TO_VPP1_SEL_IN
+	},
+	{
+		MDP_COMP_CAMIN2, MDP_COMP_PQ0_SOUT,
+		MT8195_VPPSYS0_WARP1_MOUT_EN,
+		MT8195_VPPSYS0_WARP1_MOUT_TO_PQ_SEL_IN,
+		MT8195_VPPSYS0_WARP1_MOUT_TO_PQ_SEL_IN
+	}, {
+		MDP_COMP_CAMIN2, MDP_COMP_VPP0_SOUT,
+		MT8195_VPPSYS0_WARP1_MOUT_EN,
+		MT8195_VPPSYS0_WARP1_MOUT_TO_VPP1_SEL_IN,
+		MT8195_VPPSYS0_WARP1_MOUT_TO_VPP1_SEL_IN
+	}, {
+		MDP_COMP_FG0, MDP_COMP_PQ0_SOUT,
+		MT8195_VPPSYS0_FG_MOUT_EN,
+		MT8195_VPPSYS0_FG_MOUT_TO_PQ_SEL_IN,
+		MT8195_VPPSYS0_FG_MOUT_TO_PQ_SEL_IN
+	}, {
+		MDP_COMP_FG0, MDP_COMP_VPP0_SOUT,
+		MT8195_VPPSYS0_FG_MOUT_EN,
+		MT8195_VPPSYS0_FG_MOUT_TO_VPP1_SEL_IN,
+		MT8195_VPPSYS0_FG_MOUT_TO_VPP1_SEL_IN
+	},
+	/* VPPSYS1 MOUT */
+	{
+		MDP_COMP_TO_SVPP2MOUT, MDP_COMP_HDR2,
+		MT8195_SVPP2_SRC_SEL_MOUT_EN,
+		MT8195_SVPP2_MDP_HDR,
+		MT8195_SVPP2_MDP_HDR
+	}, {
+		MDP_COMP_TO_SVPP2MOUT, MDP_COMP_HDR1,
+		MT8195_SVPP2_SRC_SEL_MOUT_EN,
+		MT8195_SVPP1_HDR_SRC_SEL,
+		MT8195_SVPP1_HDR_SRC_SEL
+	}, {
+		MDP_COMP_TO_SVPP3MOUT, MDP_COMP_HDR3,
+		MT8195_SVPP3_SRC_SEL_MOUT_EN,
+		MT8195_SVPP3_MDP_HDR,
+		MT8195_SVPP3_MDP_HDR
+	}, {
+		MDP_COMP_TO_SVPP3MOUT, MDP_COMP_VPP1_SOUT,
+		MT8195_SVPP3_SRC_SEL_MOUT_EN,
+		MT8195_VPP0_DL1_SRC_SEL,
+		MT8195_VPP0_DL1_SRC_SEL
+	}, {
+		MDP_COMP_HDR2, MDP_COMP_AAL2,
+		MT8195_SVPP2_MDP_HDR_MOUT_EN,
+		MT8195_SVPP2_MDP_AAL,
+		MT8195_SVPP2_MDP_AAL
+	}, {
+		MDP_COMP_HDR2, MDP_COMP_AAL1,
+		MT8195_SVPP2_MDP_HDR_MOUT_EN,
+		MT8195_SVPP1_MDP_AAL_SEL,
+		MT8195_SVPP1_MDP_AAL_SEL
+	}, {
+		MDP_COMP_HDR3, MDP_COMP_AAL3,
+		MT8195_SVPP3_MDP_HDR_MOUT_EN,
+		MT8195_SVPP3_MDP_AAL,
+		MT8195_SVPP3_MDP_AAL
+	}, {
+		MDP_COMP_HDR3, MDP_COMP_VPP1_SOUT,
+		MT8195_SVPP3_MDP_HDR_MOUT_EN,
+		MT8195_VPP0_DL1_SRC_SEL,
+		MT8195_VPP0_DL1_SRC_SEL
+	},
+	/* VPPSYS0 SEL_IN */
+	{
+		MDP_COMP_STITCH, MDP_COMP_PQ0_SOUT,
+		MT8195_VPPSYS0_PQ_SEL_IN,
+		MT8195_VPPSYS0_PQ_SEL_IN_FROM_STITCH,
+		MT8195_VPPSYS0_PQ_SEL_IN_FROM_STITCH
+	}, {
+		MDP_COMP_CAMIN, MDP_COMP_PQ0_SOUT,
+		MT8195_VPPSYS0_PQ_SEL_IN,
+		MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP0,
+		MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP0
+	}, {
+		MDP_COMP_CAMIN2, MDP_COMP_PQ0_SOUT,
+		MT8195_VPPSYS0_PQ_SEL_IN,
+		MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP1,
+		MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP1
+	}, {
+		MDP_COMP_FG0, MDP_COMP_PQ0_SOUT,
+		MT8195_VPPSYS0_PQ_SEL_IN,
+		MT8195_VPPSYS0_PQ_SEL_IN_FROM_MDP_FG,
+		MT8195_VPPSYS0_PQ_SEL_IN_FROM_MDP_FG
+	}, {
+		MDP_COMP_PAD0, MDP_COMP_VPP0_SOUT,
+		MT8195_VPPSYS0_VPP1_SEL_IN,
+		MT8195_VPPSYS0_VPP1_SEL_IN_FROM_PADDING_SOUT,
+		MT8195_VPPSYS0_VPP1_SEL_IN_FROM_PADDING_SOUT
+	}, {
+		MDP_COMP_STITCH, MDP_COMP_VPP0_SOUT,
+		MT8195_VPPSYS0_VPP1_SEL_IN,
+		MT8195_VPPSYS0_VPP1_SEL_IN_FROM_STITCH,
+		MT8195_VPPSYS0_VPP1_SEL_IN_FROM_STITCH
+	}, {
+		MDP_COMP_CAMIN, MDP_COMP_VPP0_SOUT,
+		MT8195_VPPSYS0_VPP1_SEL_IN,
+		MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP0,
+		MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP0
+	}, {
+		MDP_COMP_CAMIN2, MDP_COMP_VPP0_SOUT,
+		MT8195_VPPSYS0_VPP1_SEL_IN,
+		MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP1,
+		MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP1
+	}, {
+		MDP_COMP_FG0, MDP_COMP_VPP0_SOUT,
+		MT8195_VPPSYS0_VPP1_SEL_IN,
+		MT8195_VPPSYS0_VPP1_SEL_IN_FROM_MDP_FG,
+		MT8195_VPPSYS0_VPP1_SEL_IN_FROM_MDP_FG
+	}, {
+		MDP_COMP_PQ0_SOUT, MDP_COMP_HDR0,
+		MT8195_VPPSYS0_HDR_SEL_IN,
+		MT8195_VPPSYS0_HDR_SEL_IN_FROM_PQ_SOUT,
+		MT8195_VPPSYS0_HDR_SEL_IN_FROM_PQ_SOUT
+	}, {
+		MDP_COMP_TCC0, MDP_COMP_HDR0,
+		MT8195_VPPSYS0_HDR_SEL_IN,
+		MT8195_VPPSYS0_HDR_SEL_IN_FROM_TCC_SOUT,
+		MT8195_VPPSYS0_HDR_SEL_IN_FROM_TCC_SOUT
+	}, {
+		MDP_COMP_VPP1_SOUT, MDP_COMP_HDR0,
+		MT8195_VPPSYS0_HDR_SEL_IN,
+		MT8195_VPPSYS0_HDR_SEL_IN_FROM_VPP1_IN_SOUT,
+		MT8195_VPPSYS0_HDR_SEL_IN_FROM_VPP1_IN_SOUT
+	}, {
+		MDP_COMP_HDR0, MDP_COMP_AAL0,
+		MT8195_VPPSYS0_AAL_SEL_IN,
+		MT8195_VPPSYS0_AAL_SEL_IN_FROM_MDP_HDR,
+		MT8195_VPPSYS0_AAL_SEL_IN_FROM_MDP_HDR
+	}, {
+		MDP_COMP_VPP1_SOUT, MDP_COMP_AAL0,
+		MT8195_VPPSYS0_AAL_SEL_IN,
+		MT8195_VPPSYS0_AAL_SEL_IN_FROM_VPP1_IN_SOUT,
+		MT8195_VPPSYS0_AAL_SEL_IN_FROM_VPP1_IN_SOUT
+	}, {
+		MDP_COMP_PAD0, MDP_COMP_TCC0,
+		MT8195_VPPSYS0_TCC_SEL_IN,
+		MT8195_VPPSYS0_TCC_SEL_IN_FROM_PADDING_SOUT,
+		MT8195_VPPSYS0_TCC_SEL_IN_FROM_PADDING_SOUT
+	}, {
+		MDP_COMP_PQ0_SOUT, MDP_COMP_TCC0,
+		MT8195_VPPSYS0_TCC_SEL_IN,
+		MT8195_VPPSYS0_TCC_SEL_IN_FROM_PQ_SOUT,
+		MT8195_VPPSYS0_TCC_SEL_IN_FROM_PQ_SOUT
+	}, {
+		MDP_COMP_TCC0, MDP_COMP_WROT0,
+		MT8195_VPPSYS0_WROT_SEL_IN,
+		MT8195_VPPSYS0_WROT_SEL_IN_FROM_TCC_SOUT,
+		MT8195_VPPSYS0_WROT_SEL_IN_FROM_TCC_SOUT
+	}, {
+		MDP_COMP_PAD0, MDP_COMP_WROT0,
+		MT8195_VPPSYS0_WROT_SEL_IN,
+		MT8195_VPPSYS0_WROT_SEL_IN_FROM_PADDING_SOUT,
+		MT8195_VPPSYS0_WROT_SEL_IN_FROM_PADDING_SOUT
+	}, {
+		MDP_COMP_RDMA0, MDP_COMP_WROT0,
+		MT8195_VPPSYS0_WROT_SEL_IN,
+		MT8195_VPPSYS0_WROT_SEL_IN_FROM_MDP_RDMA,
+		MT8195_VPPSYS0_WROT_SEL_IN_FROM_MDP_RDMA
+	},
+	/* VPPSYS1 SEL_IN */
+	{
+		MDP_COMP_FG1, MDP_COMP_PQ1_SOUT,
+		MT8195_SVPP1_SRC_SEL_IN,
+		MT8195_SVPP1_SRC_SEL_IN_FROM_SVPP1_MDP_FG,
+		MT8195_SVPP1_SRC_SEL_IN_FROM_SVPP1_MDP_FG
+	}, {
+		MDP_COMP_VPP0_SOUT, MDP_COMP_PQ1_SOUT,
+		MT8195_SVPP1_SRC_SEL_IN,
+		MT8195_SVPP1_SRC_SEL_IN_FROM_VPP0_SRC_SOUT,
+		MT8195_SVPP1_SRC_SEL_IN_FROM_VPP0_SRC_SOUT
+	}, {
+		MDP_COMP_FG2, MDP_COMP_TO_SVPP2MOUT,
+		MT8195_SVPP2_SRC_SEL_IN,
+		MT8195_SVPP2_SRC_SEL_IN_FROM_SVPP2_MDP_FG,
+		MT8195_SVPP2_SRC_SEL_IN_FROM_SVPP2_MDP_FG
+	}, {
+		MDP_COMP_SPLIT, MDP_COMP_TO_SVPP2MOUT,
+		MT8195_SVPP2_SRC_SEL_IN,
+		MT8195_SVPP2_SRC_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT,
+		MT8195_SVPP2_SRC_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT
+	}, {
+		MDP_COMP_FG3, MDP_COMP_TO_SVPP3MOUT,
+		MT8195_SVPP3_SRC_SEL_IN,
+		MT8195_SVPP3_SRC_SEL_IN_FROM_SVPP3_MDP_FG,
+		MT8195_SVPP3_SRC_SEL_IN_FROM_SVPP3_MDP_FG
+	}, {
+		MDP_COMP_SPLIT2, MDP_COMP_TO_SVPP3MOUT,
+		MT8195_SVPP3_SRC_SEL_IN,
+		MT8195_SVPP3_SRC_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT,
+		MT8195_SVPP3_SRC_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT
+	}, {
+		MDP_COMP_PQ1_SOUT, MDP_COMP_HDR1,
+		MT8195_SVPP1_HDR_SRC_SEL_IN,
+		MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT,
+		MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT
+	}, {
+		MDP_COMP_TCC1, MDP_COMP_HDR1,
+		MT8195_SVPP1_HDR_SRC_SEL_IN,
+		MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT,
+		MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT
+	}, {
+		MDP_COMP_TO_SVPP2MOUT, MDP_COMP_HDR1,
+		MT8195_SVPP1_HDR_SRC_SEL_IN,
+		MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP2_SRC_SEL_MOUT,
+		MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP2_SRC_SEL_MOUT
+	}, {
+		MDP_COMP_HDR1, MDP_COMP_AAL1,
+		MT8195_SVPP1_MDP_AAL_SEL_IN,
+		MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP1_MDP_HDR,
+		MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP1_MDP_HDR
+	}, {
+		MDP_COMP_HDR2, MDP_COMP_AAL1,
+		MT8195_SVPP1_MDP_AAL_SEL_IN,
+		MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP2_MDP_HDR_MOUT,
+		MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP2_MDP_HDR_MOUT
+	}, {
+		MDP_COMP_PAD1, MDP_COMP_TCC1,
+		MT8195_SVPP1_TCC_SEL_IN,
+		MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_PATH_SOUT,
+		MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_PATH_SOUT
+	}, {
+		MDP_COMP_PQ1_SOUT, MDP_COMP_TCC1,
+		MT8195_SVPP1_TCC_SEL_IN,
+		MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT,
+		MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT
+	}, {
+		MDP_COMP_TO_SVPP3MOUT, MDP_COMP_VPP1_SOUT,
+		MT8195_VPP0_DL1_SRC_SEL_IN,
+		MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_SRC_SEL_MOUT,
+		MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_SRC_SEL_MOUT
+	}, {
+		MDP_COMP_HDR3, MDP_COMP_VPP1_SOUT,
+		MT8195_VPP0_DL1_SRC_SEL_IN,
+		MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_MDP_HDR_MOUT,
+		MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_MDP_HDR_MOUT
+	}, {
+		MDP_COMP_PQ1_SOUT, MDP_COMP_VPP1_SOUT,
+		MT8195_VPP0_DL1_SRC_SEL_IN,
+		MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT,
+		MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT
+	}, {
+		MDP_COMP_AAL2, MDP_COMP_RSZ2,
+		MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN,
+		MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_SVPP2_MDP_AAL,
+		MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_SVPP2_MDP_AAL
+	}, {
+		MDP_COMP_SPLIT, MDP_COMP_RSZ2,
+		MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN,
+		MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT,
+		MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT
+	}, {
+		MDP_COMP_AAL3, MDP_COMP_RSZ3,
+		MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN,
+		MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_SVPP3_MDP_AAL,
+		MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_SVPP3_MDP_AAL
+	}, {
+		MDP_COMP_SPLIT2, MDP_COMP_RSZ3,
+		MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN,
+		MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT,
+		MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT
+	}, {
+		MDP_COMP_TCC1, MDP_COMP_WROT1,
+		MT8195_SVPP1_WROT_SRC_SEL_IN,
+		MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT,
+		MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT
+	}, {
+		MDP_COMP_PAD1, MDP_COMP_WROT1,
+		MT8195_SVPP1_WROT_SRC_SEL_IN,
+		MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT,
+		MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT
+	}, {
+		MDP_COMP_RDMA1, MDP_COMP_WROT1,
+		MT8195_SVPP1_WROT_SRC_SEL_IN,
+		MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_MDP_RDMA_SOUT,
+		MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_MDP_RDMA_SOUT
+	}, {
+		MDP_COMP_PAD1, MDP_COMP_WROT2,
+		MT8195_SVPP2_WROT_SRC_SEL_IN,
+		MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT,
+		MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT
+	}, {
+		MDP_COMP_PAD2, MDP_COMP_WROT2,
+		MT8195_SVPP2_WROT_SRC_SEL_IN,
+		MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_VPP_PAD,
+		MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_VPP_PAD
+	}, {
+		MDP_COMP_RDMA2, MDP_COMP_WROT2,
+		MT8195_SVPP2_WROT_SRC_SEL_IN,
+		MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_MDP_RDMA_SOUT,
+		MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_MDP_RDMA_SOUT
+	}, {
+		MDP_COMP_VPP0_SOUT, MDP_COMP_WROT3,
+		MT8195_SVPP3_WROT_SRC_SEL_IN,
+		MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_VPP0_SRC_SOUT,
+		MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_VPP0_SRC_SOUT
+	}, {
+		MDP_COMP_PAD3, MDP_COMP_WROT3,
+		MT8195_SVPP3_WROT_SRC_SEL_IN,
+		MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_VPP_PAD,
+		MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_VPP_PAD
+	}, {
+		MDP_COMP_RDMA3, MDP_COMP_WROT3,
+		MT8195_SVPP3_WROT_SRC_SEL_IN,
+		MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_MDP_RDMA_SOUT,
+		MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_MDP_RDMA_SOUT
+	},
+	/* VPPSYS0 SEL_OUT */
+	{
+		MDP_COMP_WPEI, MDP_COMP_STITCH,
+		MT8195_VPPSYS0_WARP0_SOUT_SEL_IN,
+		MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH,
+		MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH
+	}, {
+		MDP_COMP_WPEI, MDP_COMP_CAMIN,
+		MT8195_VPPSYS0_WARP0_SOUT_SEL_IN,
+		MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP0_MOUT,
+		MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP0_MOUT
+	}, {
+		MDP_COMP_WPEI2, MDP_COMP_STITCH,
+		MT8195_VPPSYS0_WARP1_SOUT_SEL_IN,
+		MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH,
+		MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH
+	}, {
+		MDP_COMP_WPEI2, MDP_COMP_CAMIN2,
+		MT8195_VPPSYS0_WARP1_SOUT_SEL_IN,
+		MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP1_MOUT,
+		MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP1_MOUT
+	}, {
+		MDP_COMP_RDMA0, MDP_COMP_FG0,
+		MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN,
+		MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_FG,
+		MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_FG
+	}, {
+		MDP_COMP_RDMA0, MDP_COMP_WROT0,
+		MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN,
+		MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_WROT_SEL_IN,
+		MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_WROT_SEL_IN
+	}, {
+		MDP_COMP_PQ0_SOUT, MDP_COMP_HDR0,
+		MT8195_VPPSYS0_PQ_SOUT_SEL_IN,
+		MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_PQ_SEL_IN,
+		MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_PQ_SEL_IN
+	}, {
+		MDP_COMP_PQ0_SOUT, MDP_COMP_TCC0,
+		MT8195_VPPSYS0_PQ_SOUT_SEL_IN,
+		MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_TCC_SEL_IN,
+		MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_TCC_SEL_IN
+	}, {
+		MDP_COMP_VPP1_SOUT, MDP_COMP_HDR0,
+		MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN,
+		MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_HDR_SEL_IN,
+		MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_HDR_SEL_IN
+	}, {
+		MDP_COMP_VPP1_SOUT, MDP_COMP_AAL0,
+		MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN,
+		MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_AAL_SEL_IN,
+		MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_AAL_SEL_IN
+	}, {
+		MDP_COMP_VPP1_SOUT, MDP_COMP_RSZ2,
+		MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN,
+		MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_MDP_RSZ,
+		MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_MDP_RSZ
+	}, {
+		MDP_COMP_PAD0, MDP_COMP_TCC0,
+		MT8195_VPPSYS0_PADDING_SOUT_SEL_IN,
+		MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_TCC_SEL_IN,
+		MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_TCC_SEL_IN
+	}, {
+		MDP_COMP_PAD0, MDP_COMP_WROT0,
+		MT8195_VPPSYS0_PADDING_SOUT_SEL_IN,
+		MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_WROT_SEL_IN,
+		MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_WROT_SEL_IN
+	}, {
+		MDP_COMP_PAD0, MDP_COMP_VPP0_SOUT,
+		MT8195_VPPSYS0_PADDING_SOUT_SEL_IN,
+		MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_VPP1_SEL_IN,
+		MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_VPP1_SEL_IN
+	}, {
+		MDP_COMP_TCC0, MDP_COMP_WROT0,
+		MT8195_VPPSYS0_TCC_SOUT_SEL_IN,
+		MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_WROT_SEL_IN,
+		MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_WROT_SEL_IN
+	}, {
+		MDP_COMP_TCC0, MDP_COMP_HDR0,
+		MT8195_VPPSYS0_TCC_SOUT_SEL_IN,
+		MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_HDR_SEL_IN,
+		MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_HDR_SEL_IN
+	},
+	/* VPPSYS1 SEL_OUT */
+	{
+		MDP_COMP_RDMA1, MDP_COMP_FG1,
+		MT8195_SVPP1_MDP_RDMA_SOUT_SEL,
+		MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_MDP_FG,
+		MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_MDP_FG
+	}, {
+		MDP_COMP_RDMA1, MDP_COMP_RSZ2,
+		MT8195_SVPP1_MDP_RDMA_SOUT_SEL,
+		MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_RSZ,
+		MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_RSZ
+	}, {
+		MDP_COMP_RDMA1, MDP_COMP_WROT1,
+		MT8195_SVPP1_MDP_RDMA_SOUT_SEL,
+		MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL,
+		MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL
+	}, {
+		MDP_COMP_RDMA2, MDP_COMP_FG2,
+		MT8195_SVPP2_MDP_RDMA_SOUT_SEL,
+		MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_FG,
+		MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_FG
+	}, {
+		MDP_COMP_RDMA2, MDP_COMP_WROT2,
+		MT8195_SVPP2_MDP_RDMA_SOUT_SEL,
+		MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL,
+		MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL
+	}, {
+		MDP_COMP_RDMA3, MDP_COMP_FG3,
+		MT8195_SVPP3_MDP_RDMA_SOUT_SEL,
+		MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_MDP_FG,
+		MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_MDP_FG
+	}, {
+		MDP_COMP_RDMA3, MDP_COMP_WROT3,
+		MT8195_SVPP3_MDP_RDMA_SOUT_SEL,
+		MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL,
+		MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL
+	}, {
+		MDP_COMP_VPP0_SOUT, MDP_COMP_PQ1_SOUT,
+		MT8195_VPP0_SRC_SOUT_SEL,
+		MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP1_SRC_SEL,
+		MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP1_SRC_SEL
+	}, {
+		MDP_COMP_VPP0_SOUT, MDP_COMP_RSZ3,
+		MT8195_VPP0_SRC_SOUT_SEL,
+		MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_MDP_RSZ,
+		MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_MDP_RSZ
+	}, {
+		MDP_COMP_VPP0_SOUT, MDP_COMP_WROT3,
+		MT8195_VPP0_SRC_SOUT_SEL,
+		MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL,
+		MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL
+	}, {
+		MDP_COMP_PQ1_SOUT, MDP_COMP_HDR1,
+		MT8195_SVPP1_SRC_SEL_SOUT_SEL,
+		MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL,
+		MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL
+	}, {
+		MDP_COMP_PQ1_SOUT, MDP_COMP_TCC1,
+		MT8195_SVPP1_SRC_SEL_SOUT_SEL,
+		MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_TCC_SEL,
+		MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_TCC_SEL
+	}, {
+		MDP_COMP_PQ1_SOUT, MDP_COMP_VPP1_SOUT,
+		MT8195_SVPP1_SRC_SEL_SOUT_SEL,
+		MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_VPP0_DL1_SRC_SEL,
+		MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_VPP0_DL1_SRC_SEL
+	}, {
+		MDP_COMP_COLOR2, MDP_COMP_PAD2,
+		MT8195_SVPP2_COLOR_SOUT_SEL,
+		MT8195_SVPP2_COLOR_SOUT_SEL_TO_SVPP2_VPP_PAD,
+		MT8195_SVPP2_COLOR_SOUT_SEL_TO_SVPP2_VPP_PAD
+	}, {
+		MDP_COMP_COLOR2, MDP_COMP_VDO0DL0,
+		MT8195_SVPP2_COLOR_SOUT_SEL,
+		MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO0_DL0_RELAY,
+		MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO0_DL0_RELAY
+	}, {
+		MDP_COMP_COLOR2, MDP_COMP_VDO1DL0,
+		MT8195_SVPP2_COLOR_SOUT_SEL,
+		MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO1_DL0_RELAY,
+		MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO1_DL0_RELAY
+	}, {
+		MDP_COMP_COLOR3, MDP_COMP_PAD3,
+		MT8195_SVPP3_COLOR_SOUT_SEL,
+		MT8195_SVPP3_COLOR_SOUT_SEL_TO_SVPP3_VPP_PAD,
+		MT8195_SVPP3_COLOR_SOUT_SEL_TO_SVPP3_VPP_PAD
+	}, {
+		MDP_COMP_COLOR3, MDP_COMP_VDO0DL1,
+		MT8195_SVPP3_COLOR_SOUT_SEL,
+		MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO0_DL1_RELAY,
+		MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO0_DL1_RELAY
+	}, {
+		MDP_COMP_COLOR3, MDP_COMP_VDO1DL1,
+		MT8195_SVPP3_COLOR_SOUT_SEL,
+		MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO1_DL1_RELAY,
+		MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO1_DL1_RELAY
+	}, {
+		MDP_COMP_TCC1, MDP_COMP_WROT1,
+		MT8195_SVPP1_TCC_SOUT_SEL,
+		MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL,
+		MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL
+	}, {
+		MDP_COMP_TCC1, MDP_COMP_HDR1,
+		MT8195_SVPP1_TCC_SOUT_SEL,
+		MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL,
+		MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL
+	}, {
+		MDP_COMP_PAD1, MDP_COMP_TCC1,
+		MT8195_SVPP1_PATH_SOUT_SEL,
+		MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_TCC_SEL,
+		MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_TCC_SEL
+	}, {
+		MDP_COMP_PAD1, MDP_COMP_WROT1,
+		MT8195_SVPP1_PATH_SOUT_SEL,
+		MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL,
+		MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL
+	}, {
+		MDP_COMP_PAD1, MDP_COMP_WROT2,
+		MT8195_SVPP1_PATH_SOUT_SEL,
+		MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL,
+		MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL
+	},
+};
+
 #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index cbae8063a187..f73ed33258b9 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -69,6 +69,24 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
 	.clk_driver = "clk-mt8195-vdo1",
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = {
+	.clk_driver = "clk-mt8195-vpp0",
+	.mdp_routes = mmsys_mt8195_mdp_routing_table,
+	.mdp_num_routes = ARRAY_SIZE(mmsys_mt8195_mdp_routing_table),
+	.mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
+	.mdp_num_mmsys_configs = ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
+	.vppsys = true,
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
+	.clk_driver = "clk-mt8195-vpp1",
+	.mdp_routes = mmsys_mt8195_mdp_routing_table,
+	.mdp_num_routes = ARRAY_SIZE(mmsys_mt8195_mdp_routing_table),
+	.mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
+	.mdp_num_mmsys_configs = ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
+	.vppsys = true,
+};
+
 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
 	.clk_driver = "clk-mt8365-mm",
 	.routes = mt8365_mmsys_routing_table,
@@ -263,6 +281,18 @@ void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
 
+void mtk_mmsys_write_reg(struct device *dev,
+			 struct mmsys_cmdq_cmd *cmd,
+			 u32 alias_id, u32 value, u32 mask)
+{
+	struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+	const u32 *configs = mmsys->data->mdp_mmsys_configs;
+
+	cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
+			    mmsys->addr + configs[alias_id], value, mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg);
+
 static int mtk_mmsys_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -301,6 +331,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 	if (IS_ERR(clks))
 		return PTR_ERR(clks);
 
+	if (mmsys->data->vppsys)
+		goto exit;
+
 	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
 					    PLATFORM_DEVID_AUTO, NULL, 0);
 	if (IS_ERR(drm)) {
@@ -308,6 +341,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return PTR_ERR(drm);
 	}
 
+exit:
 	return 0;
 }
 
@@ -348,6 +382,14 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
 		.compatible = "mediatek,mt8195-vdosys1",
 		.data = &mt8195_vdosys1_driver_data,
 	},
+	{
+		.compatible = "mediatek,mt8195-vppsys0",
+		.data = &mt8195_vppsys0_driver_data,
+	},
+	{
+		.compatible = "mediatek,mt8195-vppsys1",
+		.data = &mt8195_vppsys1_driver_data,
+	},
 	{
 		.compatible = "mediatek,mt8365-mmsys",
 		.data = &mt8365_mmsys_driver_data,
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index b24da589ff64..e52a6ff8c843 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -93,6 +93,9 @@ struct mtk_mmsys_driver_data {
 	const struct		mtk_mmsys_routes *mdp_routes;
 	const unsigned int	mdp_num_routes;
 	const unsigned int	*mdp_isp_ctrl;
+	const u32 *mdp_mmsys_configs;
+	const unsigned int mdp_num_mmsys_configs;
+	bool vppsys;
 };
 
 /*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index acf4bd3deac1..ab20aaab6b4b 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -191,4 +191,8 @@ void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
 			      enum mtk_mdp_comp_id id,
 			      u32 camin_w, u32 camin_h);
 
+void mtk_mmsys_write_reg(struct device *dev,
+			 struct mmsys_cmdq_cmd *cmd,
+			 u32 alias_id, u32 value, u32 mask);
+
 #endif /* __MTK_MMSYS_H */
