From patchwork Tue Nov 30 03:35:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12646289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2998AC433F5 for ; Tue, 30 Nov 2021 03:48:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VdhNQjk/3za56PS7EVWGt7tC5r0N24rAI4NF02+oAGo=; b=a3OzdytLTGaKVg f/buDA9cSzxQfYRZXBRjZBsuQt9DWRsYdG2bu17ScWDJGCBANdsmWB9XhQ2ZwU+tMAvK/rPBRaAMq zCpla6uuYJYXVthZfvkbDi4lcYb+I+/feNW8VuCNW4V1aXnA9PpgHckJSfYF1ZXenjEmZLH+iNpoS FhLquZ1ivKP2tHqKP8H6T2UqVgfnbqA2ZPp6qiPIq6ASNR3mEW2MaDACOTRqLQ98vmQVj2xMYkUlt nNgLLhPl/BAO+eB0ClLjgSiE0x5Msq5+6/25t//ausXEvAB7Um7/K2uZ+uQfp7kW8bTXqWaXQemuF yienTaK9fF0l4Id0q/dg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mru7q-003TMH-0P; Tue, 30 Nov 2021 03:48:14 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mru5N-003S8l-FL; Tue, 30 Nov 2021 03:45:43 +0000 X-UUID: 6550cefbe7394d34aad0d0eebff49cbe-20211129 X-UUID: 6550cefbe7394d34aad0d0eebff49cbe-20211129 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 694642178; Mon, 29 Nov 2021 20:45:29 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 29 Nov 2021 19:35:30 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 30 Nov 2021 11:35:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 30 Nov 2021 11:35:23 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v9 07/22] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1 Date: Tue, 30 Nov 2021 11:35:04 +0800 Message-ID: <20211130033519.26086-8-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211130033519.26086-1-nancy.lin@mediatek.com> References: <20211130033519.26086-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211129_194541_569252_539B6DBC X-CRM114-Status: GOOD ( 18.79 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add cmdq support for mtk-mmsys config API. The mmsys config register settings need to take effect with the other HW settings(like OVL_ADAPTOR...) at the same vblanking time. If we use CPU to write the mmsys reg, we can't guarantee all the settings can be written in the same vblanking time. Cmdq is used for this purpose. We prepare all the related HW settings in one cmdq packet. The first command in the packet is "wait stream done", and then following with all the HW settings. After the cmdq packet is flush to GCE HW. The GCE waits for the "stream done event" to coming and then starts flushing all the HW settings. This can guarantee all the settings flush in the same vblanking. Signed-off-by: Nancy.Lin --- drivers/soc/mediatek/mtk-mmsys.c | 29 ++++++++++++++++++++------ include/linux/soc/mediatek/mtk-mmsys.h | 6 +++++- 2 files changed, 28 insertions(+), 7 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 725a99fcbc6d..1b0024ee47a9 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -88,6 +88,7 @@ struct mtk_mmsys { const struct mtk_mmsys_driver_data *data; spinlock_t lock; /* protects mmsys_sw_rst_b reg */ struct reset_controller_dev rcdev; + struct cmdq_client_reg cmdq_base; }; void mtk_mmsys_ddp_connect(struct device *dev, @@ -180,7 +181,7 @@ static const struct reset_control_ops mtk_mmsys_reset_ops = { }; void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, - u32 id, u32 val) + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt) { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); const struct mtk_mmsys_config *mmsys_config = mmsys->data->config; @@ -188,7 +189,6 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, u32 mask; u32 offset; int i; - u32 tmp; if (!mmsys->data->num_configs) return; @@ -204,10 +204,20 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, mask = mmsys_config[i].mask; reg_val = val << mmsys_config[i].shift; - tmp = readl(mmsys->regs + offset); - - tmp = (tmp & ~mask) | reg_val; - writel(tmp, mmsys->regs + offset); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + if (cmdq_pkt && mmsys->cmdq_base.size) { + cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, + mmsys->cmdq_base.offset + offset, reg_val, + mask); + } else { +#endif + u32 tmp = readl(mmsys->regs + offset); + + tmp = (tmp & ~mask) | reg_val; + writel(tmp, mmsys->regs + offset); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + } +#endif } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config); @@ -243,6 +253,13 @@ static int mtk_mmsys_probe(struct platform_device *pdev) } mmsys->data = of_device_get_match_data(&pdev->dev); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); + if (ret) + dev_dbg(dev, "No mediatek,gce-client-reg!\n"); +#endif + platform_set_drvdata(pdev, mmsys); clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index b2d2310d7e7a..3e998bfb795a 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -6,6 +6,10 @@ #ifndef __MTK_MMSYS_H #define __MTK_MMSYS_H +#include +#include +#include + enum mtk_ddp_comp_id; struct device; @@ -78,6 +82,6 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, enum mtk_ddp_comp_id next); void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, - u32 id, u32 val); + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt); #endif /* __MTK_MMSYS_H */