diff mbox series

[v11,2/3] dts: arm64: mt8183: add Mediatek MDP3 nodes

Message ID 20220105093758.6850-3-moudy.ho@mediatek.com (mailing list archive)
State New, archived
Headers show
Series media: mediatek: support mdp3 on mt8183 platform | expand

Commit Message

Moudy Ho (何宗原) Jan. 5, 2022, 9:37 a.m. UTC 
Add device nodes for Media Data Path 3 (MDP3) modules.

Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 108 ++++++++++++++++++++++-
 1 file changed, 107 insertions(+), 1 deletion(-)

Comments

AngeloGioacchino Del Regno Jan. 21, 2022, 11:58 a.m. UTC | #1 
Il 05/01/22 10:37, Moudy Ho ha scritto:
> Add device nodes for Media Data Path 3 (MDP3) modules.
> 
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8183.dtsi | 108 ++++++++++++++++++++++-
>   1 file changed, 107 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index ba4584faca5a..b872ef1ff6b3 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -1325,6 +1325,79 @@
>   			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>   		};
>   
> +		mdp3_rdma0: mdp3_rdma0@14001000 {
> +			compatible = "mediatek,mt8183-mdp3",
> +				     "mediatek,mt8183-mdp3-rdma0";
> +			mediatek,scp = <&scp>;
> +			mediatek,mdp3-comps = "mediatek,mt8183-mdp3-dl1",
> +					      "mediatek,mt8183-mdp3-dl2",
> +					      "mediatek,mt8183-mdp3-path1",
> +					      "mediatek,mt8183-mdp3-path2",
> +					      "mediatek,mt8183-mdp3-imgi",
> +					      "mediatek,mt8183-mdp3-exto";
> +			reg = <0 0x14001000 0 0x1000>,
> +			      <0 0x14000000 0 0x1000>,
> +			      <0 0x14005000 0 0x1000>,
> +			      <0 0x14006000 0 0x1000>,
> +			      <0 0x15020000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
> +						  <&gce SUBSYS_1400XXXX 0 0x1000>,
> +						  <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
> +						  <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
> +						  <&gce SUBSYS_1502XXXX 0 0x1000>;
> +			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> +				 <&mmsys CLK_MM_MDP_RSZ1>,
> +				 <&mmsys CLK_MM_MDP_DL_TXCK>,
> +				 <&mmsys CLK_MM_MDP_DL_RX>,
> +				 <&mmsys CLK_MM_IPU_DL_TXCK>,
> +				 <&mmsys CLK_MM_IPU_DL_RX>;
> +			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
> +			mediatek,mmsys = <&mmsys>;
> +			mediatek,mm-mutex = <&mutex>;
> +			mediatek,mailbox-gce = <&gce>;
> +			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
> +				 <&gce 21 CMDQ_THR_PRIO_LOWEST>,
> +				 <&gce 22 CMDQ_THR_PRIO_LOWEST>,
> +				 <&gce 23 CMDQ_THR_PRIO_LOWEST>;

Hello Moudy,
the mboxes for gce 21, 22, 23 are missing the third cell. Please fix.

Regards,
Angelo

> +			gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
> +				     <&gce 0x14010000 SUBSYS_1401XXXX>,
> +				     <&gce 0x14020000 SUBSYS_1402XXXX>,
> +				     <&gce 0x15020000 SUBSYS_1502XXXX>;
> +		};
> +
Moudy Ho (何宗原) Jan. 25, 2022, 8:20 a.m. UTC | #2 
On Fri, 2022-01-21 at 12:58 +0100, AngeloGioacchino Del Regno wrote:
> Il 05/01/22 10:37, Moudy Ho ha scritto:
> > Add device nodes for Media Data Path 3 (MDP3) modules.
> > 
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8183.dtsi | 108
> > ++++++++++++++++++++++-
> >   1 file changed, 107 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > index ba4584faca5a..b872ef1ff6b3 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > @@ -1325,6 +1325,79 @@
> >   			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0 0x1000>;
> >   		};
> >   
> > +		mdp3_rdma0: mdp3_rdma0@14001000 {
> > +			compatible = "mediatek,mt8183-mdp3",
> > +				     "mediatek,mt8183-mdp3-rdma0";
> > +			mediatek,scp = <&scp>;
> > +			mediatek,mdp3-comps = "mediatek,mt8183-mdp3-
> > dl1",
> > +					      "mediatek,mt8183-mdp3-
> > dl2",
> > +					      "mediatek,mt8183-mdp3-
> > path1",
> > +					      "mediatek,mt8183-mdp3-
> > path2",
> > +					      "mediatek,mt8183-mdp3-
> > imgi",
> > +					      "mediatek,mt8183-mdp3-
> > exto";
> > +			reg = <0 0x14001000 0 0x1000>,
> > +			      <0 0x14000000 0 0x1000>,
> > +			      <0 0x14005000 0 0x1000>,
> > +			      <0 0x14006000 0 0x1000>,
> > +			      <0 0x15020000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x1000 0x1000>,
> > +						  <&gce SUBSYS_1400XXXX
> > 0 0x1000>,
> > +						  <&gce SUBSYS_1400XXXX
> > 0x5000 0x1000>,
> > +						  <&gce SUBSYS_1400XXXX
> > 0x6000 0x1000>,
> > +						  <&gce SUBSYS_1502XXXX
> > 0 0x1000>;
> > +			power-domains = <&spm
> > MT8183_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> > +				 <&mmsys CLK_MM_MDP_RSZ1>,
> > +				 <&mmsys CLK_MM_MDP_DL_TXCK>,
> > +				 <&mmsys CLK_MM_MDP_DL_RX>,
> > +				 <&mmsys CLK_MM_IPU_DL_TXCK>,
> > +				 <&mmsys CLK_MM_IPU_DL_RX>;
> > +			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
> > +			mediatek,mmsys = <&mmsys>;
> > +			mediatek,mm-mutex = <&mutex>;
> > +			mediatek,mailbox-gce = <&gce>;
> > +			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
> > +				 <&gce 21 CMDQ_THR_PRIO_LOWEST>,
> > +				 <&gce 22 CMDQ_THR_PRIO_LOWEST>,
> > +				 <&gce 23 CMDQ_THR_PRIO_LOWEST>;
> 
> Hello Moudy,
> the mboxes for gce 21, 22, 23 are missing the third cell. Please fix.
> 
> Regards,
> Angelo

Hi Angelo,
Thanks for the reminder, but I'm a bit confused, the previous
version(v10) mentioned that the current upstream mbox has only 2
cells.
So I should follow this rule to remove the extra 0 in the first item as
follows:
 +			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
 +				 <&gce 21 CMDQ_THR_PRIO_LOWEST>,
 +				 <&gce 22 CMDQ_THR_PRIO_LOWEST>,
 +				 <&gce 23 CMDQ_THR_PRIO_LOWEST>;

Thanks,
Moudy Ho
> 
> > +			gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
> > +				     <&gce 0x14010000 SUBSYS_1401XXXX>,
> > +				     <&gce 0x14020000 SUBSYS_1402XXXX>,
> > +				     <&gce 0x15020000 SUBSYS_1502XXXX>;
> > +		};
> > +
> 
>
AngeloGioacchino Del Regno Jan. 27, 2022, 10:57 a.m. UTC | #3 
Il 25/01/22 09:20, moudy ho ha scritto:
> On Fri, 2022-01-21 at 12:58 +0100, AngeloGioacchino Del Regno wrote:
>> Il 05/01/22 10:37, Moudy Ho ha scritto:
>>> Add device nodes for Media Data Path 3 (MDP3) modules.
>>>
>>> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt8183.dtsi | 108
>>> ++++++++++++++++++++++-
>>>    1 file changed, 107 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>> index ba4584faca5a..b872ef1ff6b3 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>> @@ -1325,6 +1325,79 @@
>>>    			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
>>> 0 0x1000>;
>>>    		};
>>>    
>>> +		mdp3_rdma0: mdp3_rdma0@14001000 {
>>> +			compatible = "mediatek,mt8183-mdp3",
>>> +				     "mediatek,mt8183-mdp3-rdma0";
>>> +			mediatek,scp = <&scp>;
>>> +			mediatek,mdp3-comps = "mediatek,mt8183-mdp3-
>>> dl1",
>>> +					      "mediatek,mt8183-mdp3-
>>> dl2",
>>> +					      "mediatek,mt8183-mdp3-
>>> path1",
>>> +					      "mediatek,mt8183-mdp3-
>>> path2",
>>> +					      "mediatek,mt8183-mdp3-
>>> imgi",
>>> +					      "mediatek,mt8183-mdp3-
>>> exto";
>>> +			reg = <0 0x14001000 0 0x1000>,
>>> +			      <0 0x14000000 0 0x1000>,
>>> +			      <0 0x14005000 0 0x1000>,
>>> +			      <0 0x14006000 0 0x1000>,
>>> +			      <0 0x15020000 0 0x1000>;
>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
>>> 0x1000 0x1000>,
>>> +						  <&gce SUBSYS_1400XXXX
>>> 0 0x1000>,
>>> +						  <&gce SUBSYS_1400XXXX
>>> 0x5000 0x1000>,
>>> +						  <&gce SUBSYS_1400XXXX
>>> 0x6000 0x1000>,
>>> +						  <&gce SUBSYS_1502XXXX
>>> 0 0x1000>;
>>> +			power-domains = <&spm
>>> MT8183_POWER_DOMAIN_DISP>;
>>> +			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
>>> +				 <&mmsys CLK_MM_MDP_RSZ1>,
>>> +				 <&mmsys CLK_MM_MDP_DL_TXCK>,
>>> +				 <&mmsys CLK_MM_MDP_DL_RX>,
>>> +				 <&mmsys CLK_MM_IPU_DL_TXCK>,
>>> +				 <&mmsys CLK_MM_IPU_DL_RX>;
>>> +			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
>>> +			mediatek,mmsys = <&mmsys>;
>>> +			mediatek,mm-mutex = <&mutex>;
>>> +			mediatek,mailbox-gce = <&gce>;
>>> +			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
>>> +				 <&gce 21 CMDQ_THR_PRIO_LOWEST>,
>>> +				 <&gce 22 CMDQ_THR_PRIO_LOWEST>,
>>> +				 <&gce 23 CMDQ_THR_PRIO_LOWEST>;
>>
>> Hello Moudy,
>> the mboxes for gce 21, 22, 23 are missing the third cell. Please fix.
>>
>> Regards,
>> Angelo
> 
> Hi Angelo,
> Thanks for the reminder, but I'm a bit confused, the previous
> version(v10) mentioned that the current upstream mbox has only 2
> cells.
> So I should follow this rule to remove the extra 0 in the first item as
> follows:
>   +			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
>   +				 <&gce 21 CMDQ_THR_PRIO_LOWEST>,
>   +				 <&gce 22 CMDQ_THR_PRIO_LOWEST>,
>   +				 <&gce 23 CMDQ_THR_PRIO_LOWEST>;
> 
> Thanks,
> Moudy Ho

Hello Moudy,
I'm sorry for this confusion and you are totally right in the proposed solution,
which is the exact opposite of what I said.

Thanks for understanding,
Angelo

>>
>>> +			gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
>>> +				     <&gce 0x14010000 SUBSYS_1401XXXX>,
>>> +				     <&gce 0x14020000 SUBSYS_1402XXXX>,
>>> +				     <&gce 0x15020000 SUBSYS_1502XXXX>;
>>> +		};
>>> +
>>
>>
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index ba4584faca5a..b872ef1ff6b3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1325,6 +1325,79 @@ 
 			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 		};
 
+		mdp3_rdma0: mdp3_rdma0@14001000 {
+			compatible = "mediatek,mt8183-mdp3",
+				     "mediatek,mt8183-mdp3-rdma0";
+			mediatek,scp = <&scp>;
+			mediatek,mdp3-comps = "mediatek,mt8183-mdp3-dl1",
+					      "mediatek,mt8183-mdp3-dl2",
+					      "mediatek,mt8183-mdp3-path1",
+					      "mediatek,mt8183-mdp3-path2",
+					      "mediatek,mt8183-mdp3-imgi",
+					      "mediatek,mt8183-mdp3-exto";
+			reg = <0 0x14001000 0 0x1000>,
+			      <0 0x14000000 0 0x1000>,
+			      <0 0x14005000 0 0x1000>,
+			      <0 0x14006000 0 0x1000>,
+			      <0 0x15020000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
+						  <&gce SUBSYS_1400XXXX 0 0x1000>,
+						  <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
+						  <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
+						  <&gce SUBSYS_1502XXXX 0 0x1000>;
+			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+				 <&mmsys CLK_MM_MDP_RSZ1>,
+				 <&mmsys CLK_MM_MDP_DL_TXCK>,
+				 <&mmsys CLK_MM_MDP_DL_RX>,
+				 <&mmsys CLK_MM_IPU_DL_TXCK>,
+				 <&mmsys CLK_MM_IPU_DL_RX>;
+			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+			mediatek,mmsys = <&mmsys>;
+			mediatek,mm-mutex = <&mutex>;
+			mediatek,mailbox-gce = <&gce>;
+			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+				 <&gce 21 CMDQ_THR_PRIO_LOWEST>,
+				 <&gce 22 CMDQ_THR_PRIO_LOWEST>,
+				 <&gce 23 CMDQ_THR_PRIO_LOWEST>;
+			gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
+				     <&gce 0x14010000 SUBSYS_1401XXXX>,
+				     <&gce 0x14020000 SUBSYS_1402XXXX>,
+				     <&gce 0x15020000 SUBSYS_1502XXXX>;
+		};
+
+		mdp3_rsz0: mdp3_rsz0@14003000 {
+			compatible = "mediatek,mt8183-mdp3-rsz0";
+			reg = <0 0x14003000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+		};
+
+		mdp3_rsz1: mdp3_rsz1@14004000 {
+			compatible = "mediatek,mt8183-mdp3-rsz1";
+			reg = <0 0x14004000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+		};
+
+		mdp3_wrot0: mdp3_wrot0@14005000 {
+			compatible = "mediatek,mt8183-mdp3-wrot0";
+			reg = <0 0x14005000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_MDP_WROT0>;
+			iommus = <&iommu M4U_PORT_MDP_WROT0>;
+		};
+
+		mdp3_wdma: mdp3_wdma@14006000 {
+			compatible = "mediatek,mt8183-mdp3-wdma";
+			reg = <0 0x14006000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+			iommus = <&iommu M4U_PORT_MDP_WDMA0>;
+		};
+
 		ovl0: ovl@14008000 {
 			compatible = "mediatek,mt8183-disp-ovl";
 			reg = <0 0x14008000 0 0x1000>;
@@ -1449,7 +1522,33 @@ 
 			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
 			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
-					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
+					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>,
+					      <CMDQ_EVENT_MDP_RDMA0_SOF>,
+					      <CMDQ_EVENT_MDP_RDMA0_EOF>,
+					      <CMDQ_EVENT_MDP_RSZ0_SOF>,
+					      <CMDQ_EVENT_MDP_RSZ1_SOF>,
+					      <CMDQ_EVENT_MDP_TDSHP_SOF>,
+					      <CMDQ_EVENT_MDP_WROT0_SOF>,
+					      <CMDQ_EVENT_MDP_WROT0_EOF>,
+					      <CMDQ_EVENT_MDP_WDMA0_SOF>,
+					      <CMDQ_EVENT_MDP_WDMA0_EOF>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
+					      <CMDQ_EVENT_WPE_A_DONE>,
+					      <CMDQ_EVENT_SPE_B_DONE>;
 		};
 
 		larb0: larb@14017000 {
@@ -1473,6 +1572,13 @@ 
 			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
 		};
 
+		mdp3_ccorr: mdp3_ccorr@1401c000 {
+			compatible = "mediatek,mt8183-mdp3-ccorr";
+			reg = <0 0x1401c000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_CCORR>;
+		};
+
 		imgsys: syscon@15020000 {
 			compatible = "mediatek,mt8183-imgsys", "syscon";
 			reg = <0 0x15020000 0 0x1000>;