deleted file mode 100644
@@ -1,76 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Mediatek display color correction
-
-maintainers:
- - Chun-Kuang Hu <chunkuang.hu@kernel.org>
- - Philipp Zabel <p.zabel@pengutronix.de>
-
-description: |
- Mediatek display color correction, namely CCORR, reproduces correct color
- on panels with different color gamut.
- CCORR device node must be siblings to the central MMSYS_CONFIG node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
- for details.
-
-properties:
- compatible:
- oneOf:
- - items:
- - const: mediatek,mt8183-disp-ccorr
- - items:
- - const: mediatek,mt8192-disp-ccorr
- - items:
- - enum:
- - mediatek,mt8195-disp-ccorr
- - enum:
- - mediatek,mt8192-disp-ccorr
-
- reg:
- maxItems: 1
-
- interrupts:
- maxItems: 1
-
- power-domains:
- description: A phandle and PM domain specifier as defined by bindings of
- the power controller specified by phandle. See
- Documentation/devicetree/bindings/power/power-domain.yaml for details.
-
- clocks:
- items:
- - description: CCORR Clock
-
- mediatek,gce-client-reg:
- description: The register of client driver can be configured by gce with
- 4 arguments defined in this property, such as phandle of gce, subsys id,
- register offset and size. Each GCE subsys id is mapping to a client
- defined in the header include/dt-bindings/gce/<chip>-gce.h.
- $ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
-
-required:
- - compatible
- - reg
- - interrupts
- - power-domains
- - clocks
-
-additionalProperties: false
-
-examples:
- - |
-
- ccorr0: ccorr@1400f000 {
- compatible = "mediatek,mt8183-disp-ccorr";
- reg = <0 0x1400f000 0 0x1000>;
- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
- clocks = <&mmsys CLK_MM_DISP_CCORR0>;
- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
- };
deleted file mode 100644
@@ -1,86 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Mediatek Write Direct Memory Access
-
-maintainers:
- - Chun-Kuang Hu <chunkuang.hu@kernel.org>
- - Philipp Zabel <p.zabel@pengutronix.de>
-
-description: |
- Mediatek Write Direct Memory Access(WDMA) component used to write
- the data into DMA.
- WDMA device node must be siblings to the central MMSYS_CONFIG node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
- for details.
-
-properties:
- compatible:
- oneOf:
- - items:
- - const: mediatek,mt8173-disp-wdma
-
- reg:
- maxItems: 1
-
- interrupts:
- maxItems: 1
-
- power-domains:
- description: A phandle and PM domain specifier as defined by bindings of
- the power controller specified by phandle. See
- Documentation/devicetree/bindings/power/power-domain.yaml for details.
-
- clocks:
- items:
- - description: WDMA Clock
-
- iommus:
- description:
- This property should point to the respective IOMMU block with master port as argument,
- see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
-
- mediatek,larb:
- description:
- This property should contain a phandle pointing to the local arbiter devices defined in
- Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
- It must sort according to the local arbiter index, like larb0, larb1, larb2...
- $ref: /schemas/types.yaml#/definitions/phandle-array
- minItems: 1
- maxItems: 32
-
- mediatek,gce-client-reg:
- description: The register of client driver can be configured by gce with
- 4 arguments defined in this property, such as phandle of gce, subsys id,
- register offset and size. Each GCE subsys id is mapping to a client
- defined in the header include/dt-bindings/gce/<chip>-gce.h.
- $ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
-
-required:
- - compatible
- - reg
- - interrupts
- - power-domains
- - clocks
- - iommus
-
-additionalProperties: false
-
-examples:
- - |
-
- wdma0: wdma@14011000 {
- compatible = "mediatek,mt8173-disp-wdma";
- reg = <0 0x14011000 0 0x1000>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_WDMA0>;
- iommus = <&iommu M4U_PORT_DISP_WDMA0>;
- mediatek,larb = <&larb0>;
- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
- };
similarity index 78%
rename from Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
@@ -1,22 +1,17 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,aal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Mediatek display adaptive ambient light processor
+title: Mediatek adaptive ambient light processor
maintainers:
- - Chun-Kuang Hu <chunkuang.hu@kernel.org>
- - Philipp Zabel <p.zabel@pengutronix.de>
+ - Matthias Brugger <matthias.bgg@gmail.com>
description: |
- Mediatek display adaptive ambient light processor, namely AAL,
+ Mediatek adaptive ambient light processor, namely AAL,
is responsible for backlight power saving and sunlight visibility improving.
- AAL device node must be siblings to the central MMSYS_CONFIG node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
- for details.
properties:
compatible:
@@ -10,17 +10,40 @@ maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
description: |
- Mediatek color correction with 3X3 matrix.
+ Mediatek color correction, namely CCORR, reproduces correct color
+ on panels with 3X3 matrix of different color gamut.
properties:
compatible:
- items:
- - enum:
- - mediatek,mt8183-mdp3-ccorr
+ oneOf:
+ - items:
+ - const: mediatek,mt8183-mdp3-ccorr
+ - items:
+ - const: mediatek,mt8183-disp-ccorr
+ - items:
+ - const: mediatek,mt8192-disp-ccorr
+ - items:
+ - enum:
+ - mediatek,mt8195-disp-ccorr
+ - enum:
+ - mediatek,mt8192-disp-ccorr
reg:
maxItems: 1
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: CCORR Clock
+ minItems: 1
+
mediatek,gce-client-reg:
description: The register of client driver can be configured by gce with
4 arguments defined in this property, such as phandle of gce, subsys id,
@@ -29,8 +52,10 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
- clocks:
- minItems: 1
+required:
+ - compatible
+ - reg
+ - clocks
additionalProperties: false
@@ -45,3 +70,12 @@ examples:
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
clocks = <&mmsys CLK_MM_MDP_CCORR>;
};
+
+ ccorr0: ccorr@1400f000 {
+ compatible = "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
+ };
similarity index 78%
rename from Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
@@ -1,23 +1,18 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,color.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Mediatek display color processor
+title: Mediatek color processor
maintainers:
- - Chun-Kuang Hu <chunkuang.hu@kernel.org>
- - Philipp Zabel <p.zabel@pengutronix.de>
+ - Matthias Brugger <matthias.bgg@gmail.com>
description: |
- Mediatek display color processor, namely COLOR, provides hue, luma and
- saturation adjustments to get better picture quality and to have one panel
+ Mediatek color processor, namely COLOR, provides hue, luma and saturation
+ adjustments to get better picture quality and to have one panel
resemble the other in their output characteristics.
- COLOR device node must be siblings to the central MMSYS_CONFIG node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
- for details.
properties:
compatible:
similarity index 80%
rename from Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -1,25 +1,19 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mutex.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek mutex
maintainers:
- - Chun-Kuang Hu <chunkuang.hu@kernel.org>
- - Philipp Zabel <p.zabel@pengutronix.de>
+ - Matthias Brugger <matthias.bgg@gmail.com>
description: |
Mediatek mutex, namely MUTEX, is used to send the triggers signals called
- Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
- data path or MDP data path.
+ Start Of Frame(SOF) / End Of Frame(EOF) to each sub-modules on the data path.
In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
the shadow register.
- MUTEX device node must be siblings to the central MMSYS_CONFIG node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
- for details.
properties:
compatible:
@@ -15,13 +15,18 @@ description: |
properties:
compatible:
- items:
- - enum:
- - mediatek,mt8183-mdp3-wdma
+ oneOf:
+ - items:
+ - const: mediatek,mt8183-mdp3-wdma
+ - items:
+ - const: mediatek,mt8173-disp-wdma
reg:
maxItems: 1
+ interrupts:
+ maxItems: 1
+
mediatek,gce-client-reg:
description: The register of client driver can be configured by gce with
4 arguments defined in this property, such as phandle of gce, subsys id,
@@ -31,14 +36,39 @@ properties:
maxItems: 1
power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
maxItems: 1
clocks:
+ items:
+ - description: WDMA Clock
minItems: 1
iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
maxItems: 1
+ mediatek,larb:
+ description:
+ This property should contain a phandle pointing to the local arbiter devices defined in
+ Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+ It must sort according to the local arbiter index, like larb0, larb1, larb2...
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 32
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+ - iommus
+
additionalProperties: false
examples:
@@ -56,3 +86,14 @@ examples:
clocks = <&mmsys CLK_MM_MDP_WDMA0>;
iommus = <&iommu>;
};
+
+ wdma0: wdma@14011000 {
+ compatible = "mediatek,mt8173-disp-wdma";
+ reg = <0 0x14011000 0 0x1000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+ };