Message ID | 20220113065822.11809-6-allen-kh.cheng@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Update MT8192 Clock Setting | expand |
Il 13/01/22 07:58, allen-kh.cheng ha scritto: > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com> > > When the initial devicetree for mt8192 was added in 48489980e27e ("arm64: > dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile"), the > clock driver for mt8192 was not yet upstream, so the clock property nodes > were set to the clk26m clock as a placeholder. > > Given that the clock driver has since been added through 710573dee31b ("clk: > mediatek: Add MT8192 basic clocks support"), as well as its dt-bindings > through f35f1a23e0e1 ("clk: mediatek: Add dt-bindings of MT8192 clocks") and > devicetree nodes through 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 > clock controllers"), fix the systimer clock property to point to the actual > clock. > > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com> > Reviewed-by: NĂcolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 1eb5874c09a9..4f6c4ce885af 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -312,7 +312,7 @@ "mediatek,mt6765-timer"; reg = <0 0x10017000 0 0x1000>; interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&clk26m>; + clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; clock-names = "clk13m"; };