| Message ID | 20220117070706.17853-5-biao.huang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MediaTek Ethernet Patches on MT8195 | expand |
Dear Matthias, Any comments about this dts patch? Thanks in advance. Regards! Biao On Mon, 2022-01-17 at 15:07 +0800, Biao Huang wrote: > Since there are some changes in ethernet driver: > update ethernet device node in dts to accommodate to it. > > 1. stmmac_probe_config_dt() in stmmac_platform.c will initialize > specified > parameters according to compatible string "snps,dwmac-4.20a", > then, > dwmac-mediatek.c can skip the initialization if add compatible > string > "snps,dwmac-4.20a" in eth device node. > 2. commit 882007ed7832 ("net-next: dt-binding: dwmac-mediatek: add > more > description for RMII") added rmii internal support, we should add > corresponding clocks/clocks-names in eth device node. > 3. add "snps,reset-delays-us = <0 10000 10000>;" to ensure reset > delay > can meet PHY requirement. > > Signed-off-by: Biao Huang <biao.huang@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 1 + > arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 14 +++++++++----- > 2 files changed, 10 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts > b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts > index 7d369fdd3117..11aa135aa0f3 100644 > --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts > @@ -110,6 +110,7 @@ ð { > phy-handle = <ðernet_phy0>; > mediatek,tx-delay-ps = <1530>; > snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; > + snps,reset-delays-us = <0 10000 10000>; > pinctrl-names = "default", "sleep"; > pinctrl-0 = <ð_default>; > pinctrl-1 = <ð_sleep>; > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > index a9cca9c146fd..9e850e04fffb 100644 > --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > @@ -726,7 +726,7 @@ queue2 { > }; > > eth: ethernet@1101c000 { > - compatible = "mediatek,mt2712-gmac"; > + compatible = "mediatek,mt2712-gmac", "snps,dwmac- > 4.20a"; > reg = <0 0x1101c000 0 0x1300>; > interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; > interrupt-names = "macirq"; > @@ -734,15 +734,19 @@ eth: ethernet@1101c000 { > clock-names = "axi", > "apb", > "mac_main", > - "ptp_ref"; > + "ptp_ref", > + "rmii_internal"; > clocks = <&pericfg CLK_PERI_GMAC>, > <&pericfg CLK_PERI_GMAC_PCLK>, > <&topckgen CLK_TOP_ETHER_125M_SEL>, > - <&topckgen CLK_TOP_ETHER_50M_SEL>; > + <&topckgen CLK_TOP_ETHER_50M_SEL>, > + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; > assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, > - <&topckgen CLK_TOP_ETHER_50M_SEL>; > + <&topckgen CLK_TOP_ETHER_50M_SEL>, > + <&topckgen > CLK_TOP_ETHER_50M_RMII_SEL>; > assigned-clock-parents = <&topckgen > CLK_TOP_ETHERPLL_125M>, > - <&topckgen CLK_TOP_APLL1_D3>; > + <&topckgen CLK_TOP_APLL1_D3>, > + <&topckgen > CLK_TOP_ETHERPLL_50M>; > power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; > mediatek,pericfg = <&pericfg>; > snps,axi-config = <&stmmac_axi_setup>;
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index 7d369fdd3117..11aa135aa0f3 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -110,6 +110,7 @@ ð { phy-handle = <ðernet_phy0>; mediatek,tx-delay-ps = <1530>; snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; + snps,reset-delays-us = <0 10000 10000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <ð_default>; pinctrl-1 = <ð_sleep>; diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index a9cca9c146fd..9e850e04fffb 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -726,7 +726,7 @@ queue2 { }; eth: ethernet@1101c000 { - compatible = "mediatek,mt2712-gmac"; + compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a"; reg = <0 0x1101c000 0 0x1300>; interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "macirq"; @@ -734,15 +734,19 @@ eth: ethernet@1101c000 { clock-names = "axi", "apb", "mac_main", - "ptp_ref"; + "ptp_ref", + "rmii_internal"; clocks = <&pericfg CLK_PERI_GMAC>, <&pericfg CLK_PERI_GMAC_PCLK>, <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>; + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>; + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, - <&topckgen CLK_TOP_APLL1_D3>; + <&topckgen CLK_TOP_APLL1_D3>, + <&topckgen CLK_TOP_ETHERPLL_50M>; power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; mediatek,pericfg = <&pericfg>; snps,axi-config = <&stmmac_axi_setup>;
Since there are some changes in ethernet driver: update ethernet device node in dts to accommodate to it. 1. stmmac_probe_config_dt() in stmmac_platform.c will initialize specified parameters according to compatible string "snps,dwmac-4.20a", then, dwmac-mediatek.c can skip the initialization if add compatible string "snps,dwmac-4.20a" in eth device node. 2. commit 882007ed7832 ("net-next: dt-binding: dwmac-mediatek: add more description for RMII") added rmii internal support, we should add corresponding clocks/clocks-names in eth device node. 3. add "snps,reset-delays-us = <0 10000 10000>;" to ensure reset delay can meet PHY requirement. Signed-off-by: Biao Huang <biao.huang@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 1 + arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 14 +++++++++----- 2 files changed, 10 insertions(+), 5 deletions(-)