From patchwork Wed Jan 26 09:33:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 12724819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8F47C28CF5 for ; Wed, 26 Jan 2022 09:43:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=0CV/JvQdfQzaxsM79GPL3wqpcItWWwClOZOllby4f5o=; b=liOnMDY6DS2G4K c0I3rBQATiV8TWGyAWrp3IAqApsTI2ES4kDoLp3dqd0cLTakVtqyy55DcXzgptH1LhaXUX4L8i3/A IMeLRk1YDjT8B8g5wcVRUGMf63JWASjuL+Pg+mzvkXWkWFi7WI0Bnqkxtg1/ZodLPYDMqYmz9Byw5 bL1oyTff0+q/A0vnwgqIL4fgMPmkYmp8feRqUYJJe2Fuh0jMWYvmjz3DKCPiJCrrX8+6laZmzYRei 4OV93EQk2BTeeMCbWV6IIFGOHqiapwxcz6OirhDfbCXFOljRJiPSoUNYI3nd9LbA2WVqnfUSX6ro9 zcRu++PGqR7Cjwvp5Nmw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCeph-00B2wf-2x; Wed, 26 Jan 2022 09:43:17 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCep5-00B2jp-EM; Wed, 26 Jan 2022 09:42:41 +0000 X-UUID: 582361daa07b4cb58f827eff9492381c-20220126 X-UUID: 582361daa07b4cb58f827eff9492381c-20220126 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1622613610; Wed, 26 Jan 2022 02:42:37 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 26 Jan 2022 01:34:19 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 26 Jan 2022 17:34:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 26 Jan 2022 17:34:17 +0800 From: jason-jh.lin To: Rob Herring , Linus Walleij , Matthias Brugger , AngeloGioacchino Del Regno , "Paolo Bonzini" , Sean Christopherson , , David Matlack , "Jing Zhang" , Marc Zyngier , "Bartosz Golaszewski" , Sean Wang , Tinghan Shen CC: , , , , , , , , Seiya Wang , , , , , , jason-jh.lin Subject: [PATCH] arm64: dts: mt8195: add display node for vdosys0 Date: Wed, 26 Jan 2022 17:33:40 +0800 Message-ID: <20220126093340.18792-1-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220126_014239_528699_0817F1EA X-CRM114-Status: GOOD ( 11.38 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add display node for vdosys0. Signed-off-by: jason-jh.lin --- This patch depends on series [1] [1] Add Mediatek Soc DRM (vdosys0) support for mt8195 - https://patchwork.kernel.org/project/linux-mediatek/list/?series=608548 This patch is based on [2][3][4] [2] arm64: dts: Add mediatek SoC mt8195 and evaluation board - https://patchwork.kernel.org/project/linux-mediatek/patch/20220112114724.1953-4-tinghan.shen@mediatek.com/ [3] arm64: dts: mt8195: add IOMMU and smi nodes - https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/ [4] arm64: dts: mt8195: add gce node - https://patchwork.kernel.org/project/linux-mediatek/patch/20220126090109.32143-1-jason-jh.lin@mediatek.com/ --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 123 +++++++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index d778ca598d18..cc3a9e898c77 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1067,5 +1067,128 @@ reg = <0 0x1b000000 0 0x1000>; #clock-cells = <1>; }; + + ovl0: disp_ovl@1c000000 { + compatible = "mediatek,mt8195-disp-ovl", + "mediatek,mt8192-disp-ovl"; + reg = <0 0x1c000000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + }; + + rdma0: disp_rdma@1c002000 { + compatible = "mediatek,mt8195-disp-rdma"; + reg = <0 0x1c002000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + }; + + color0: disp_color@1c003000 { + compatible = "mediatek,mt8195-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1c003000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + }; + + ccorr0: disp_ccorr@1c004000 { + compatible = "mediatek,mt8195-disp-ccorr", + "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1c004000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + }; + + aal0: disp_aal@1c005000 { + compatible = "mediatek,mt8195-disp-aal", + "mediatek,mt8173-disp-aal"; + reg = <0 0x1c005000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + }; + + gamma0: disp_gamma@1c006000 { + compatible = "mediatek,mt8195-disp-gamma", + "mediatek,mt8173-disp-gamma"; + reg = <0 0x1c006000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + }; + + dither0: disp_dither@1c007000 { + compatible = "mediatek,mt8195-disp-dither", + "mediatek,mt8183-disp-dither"; + reg = <0 0x1c007000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + }; + + dsc0: disp_dsc_wrap@1c009000 { + compatible = "mediatek,mt8195-disp-dsc"; + reg = <0 0x1c009000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; + }; + + merge0: disp_vpp_merge0@1c014000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c014000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; + mediatek,gce-client-reg = + <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; + }; + + mutex: disp_mutex0@1c016000 { + compatible = "mediatek,mt8195-disp-mutex"; + reg = <0 0x1c016000 0 0x1000>; + reg-names = "vdo0_mutex"; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + clock-names = "vdo0_mutex"; + mediatek,gce-events = + ; + }; + + vdosys0: syscon@1c01a000 { + compatible = "mediatek,mt8195-vdosys0", "syscon"; + reg = <0 0x1c01a000 0 0x1000>; + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; + #clock-cells = <1>; + }; + + vdosys1: syscon@1c100000 { + compatible = "mediatek,mt8195-vdosys1", "syscon"; + reg = <0 0x1c100000 0 0x1000>; + #clock-cells = <1>; + }; }; };