diff mbox series

[v2,09/23] arm64: dts: mt8192: Add infracfg_rst node

Message ID 20220218091633.9368-10-allen-kh.cheng@mediatek.com (mailing list archive)
State New, archived
Headers show
Series Add driver nodes for MT8192 SoC | expand

Commit Message

Allen-KH Cheng Feb. 18, 2022, 9:16 a.m. UTC 
add infracfg_rst node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

Comments

AngeloGioacchino Del Regno Feb. 18, 2022, 12:55 p.m. UTC | #1 
Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> add infracfg_rst node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

For v3, please mention that you're adding simple-mfd to allow probing the
ti,syscon-reset node.

After the commit description fix:
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
>   1 file changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f93fe3779161..a935a22babbb 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -12,6 +12,7 @@
>   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
>   #include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/ti-syscon.h>
>   
>   / {
>   	compatible = "mediatek,mt8192";
> @@ -267,10 +268,23 @@
>   			#clock-cells = <1>;
>   		};
>   
> -		infracfg: syscon@10001000 {
> -			compatible = "mediatek,mt8192-infracfg", "syscon";
> +		infracfg: infracfg@10001000 {
> +			compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
>   			reg = <0 0x10001000 0 0x1000>;
>   			#clock-cells = <1>;
> +
> +			infracfg_rst: reset-controller {
> +				compatible = "ti,syscon-reset";
> +				#reset-cells = <1>;
> +
> +				ti,reset-bits = <
> +					0x120 0 0x124 0 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> +					0x730 12 0x734 12 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> +					0x140 15 0x144 15 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> +					0x730 1 0x734 1 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> +					0x150 5 0x154 5 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> +				>;
> +			};
>   		};
>   
>   		pericfg: syscon@10003000 {
Allen-KH Cheng Feb. 21, 2022, 1:05 p.m. UTC | #2 
On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > add infracfg_rst node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> 
> For v3, please mention that you're adding simple-mfd to allow probing
> the
> ti,syscon-reset node.
> 
> After the commit description fix:
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> 

Hi Angelo,

Thanks for reminding, I will update commit message.

Do I need to also change the commit title ?

Best regards,
Allen

> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
> >   1 file changed, 16 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index f93fe3779161..a935a22babbb 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -12,6 +12,7 @@
> >   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> >   #include <dt-bindings/phy/phy.h>
> >   #include <dt-bindings/power/mt8192-power.h>
> > +#include <dt-bindings/reset/ti-syscon.h>
> >   
> >   / {
> >   	compatible = "mediatek,mt8192";
> > @@ -267,10 +268,23 @@
> >   			#clock-cells = <1>;
> >   		};
> >   
> > -		infracfg: syscon@10001000 {
> > -			compatible = "mediatek,mt8192-infracfg",
> > "syscon";
> > +		infracfg: infracfg@10001000 {
> > +			compatible = "mediatek,mt8192-infracfg",
> > "syscon", "simple-mfd";
> >   			reg = <0 0x10001000 0 0x1000>;
> >   			#clock-cells = <1>;
> > +
> > +			infracfg_rst: reset-controller {
> > +				compatible = "ti,syscon-reset";
> > +				#reset-cells = <1>;
> > +
> > +				ti,reset-bits = <
> > +					0x120 0 0x124 0 0 0	(ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> > +					0x730 12 0x734 12 0 0	(AS
> > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> > +					0x140 15 0x144 15 0 0	(AS
> > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> > +					0x730 1 0x734 1 0 0	(ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> > +					0x150 5 0x154 5 0 0	(ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> > +				>;
> > +			};
> >   		};
> >   
> >   		pericfg: syscon@10003000 {
> 
> 
>
AngeloGioacchino Del Regno Feb. 21, 2022, 3:20 p.m. UTC | #3 
Il 21/02/22 14:05, allen-kh.cheng ha scritto:
> On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno wrote:
>> Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
>>> add infracfg_rst node for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>
>> For v3, please mention that you're adding simple-mfd to allow probing
>> the
>> ti,syscon-reset node.
>>
>> After the commit description fix:
>> Reviewed-by: AngeloGioacchino Del Regno <
>> angelogioacchino.delregno@collabora.com>
>>
> 
> Hi Angelo,
> 
> Thanks for reminding, I will update commit message.
> 
> Do I need to also change the commit title ?
> 
> Best regards,
> Allen
> 

Hi Allen,

Please update only the description; the title is fine.

Thank you,
Angelo
Allen-KH Cheng Feb. 22, 2022, 5:55 a.m. UTC | #4 
On Mon, 2022-02-21 at 16:20 +0100, AngeloGioacchino Del Regno wrote:
> Il 21/02/22 14:05, allen-kh.cheng ha scritto:
> > On Fri, 2022-02-18 at 13:55 +0100, AngeloGioacchino Del Regno
> > wrote:
> > > Il 18/02/22 10:16, Allen-KH Cheng ha scritto:
> > > > add infracfg_rst node for mt8192 SoC.
> > > > 
> > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > 
> > > For v3, please mention that you're adding simple-mfd to allow
> > > probing
> > > the
> > > ti,syscon-reset node.
> > > 
> > > After the commit description fix:
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > 
> > 
> > Hi Angelo,
> > 
> > Thanks for reminding, I will update commit message.
> > 
> > Do I need to also change the commit title ?
> > 
> > Best regards,
> > Allen
> > 
> 
> Hi Allen,
> 
> Please update only the description; the title is fine.
> 
> Thank you,
> Angelo

Hi Angelo,

Ok, No problem.

Many thanks,
Allen
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f93fe3779161..a935a22babbb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -12,6 +12,7 @@ 
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/reset/ti-syscon.h>
 
 / {
 	compatible = "mediatek,mt8192";
@@ -267,10 +268,23 @@ 
 			#clock-cells = <1>;
 		};
 
-		infracfg: syscon@10001000 {
-			compatible = "mediatek,mt8192-infracfg", "syscon";
+		infracfg: infracfg@10001000 {
+			compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+
+			infracfg_rst: reset-controller {
+				compatible = "ti,syscon-reset";
+				#reset-cells = <1>;
+
+				ti,reset-bits = <
+					0x120 0 0x124 0 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
+					0x730 12 0x734 12 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
+					0x140 15 0x144 15 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
+					0x730 1 0x734 1 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
+					0x150 5 0x154 5 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
+				>;
+			};
 		};
 
 		pericfg: syscon@10003000 {