Message ID | 20220218091633.9368-3-allen-kh.cheng@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add driver nodes for MT8192 SoC | expand |
Il 18/02/22 10:16, Allen-KH Cheng ha scritto: > Add pwrap node for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index f10a9c75b20c..f58a13b10916 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -523,6 +523,18 @@ > clock-names = "clk13m"; > }; > > + pwrap: pwrap@10026000 { > + compatible = "mediatek,mt6873-pwrap"; > + reg = <0 0x10026000 0 0x1000>; > + reg-names = "pwrap"; > + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&infracfg CLK_INFRA_PMIC_AP>, > + <&infracfg CLK_INFRA_PMIC_TMR>; > + clock-names = "spi", "wrap"; > + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; > + }; > + > scp_adsp: clock-controller@10720000 { > compatible = "mediatek,mt8192-scp_adsp"; > reg = <0 0x10720000 0 0x1000>;
On Fri, Feb 18, 2022 at 05:16:12PM +0800, Allen-KH Cheng wrote: > Add pwrap node for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: NĂcolas F. R. A. Prado <nfraprado@collabora.com>
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index f10a9c75b20c..f58a13b10916 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -523,6 +523,18 @@ clock-names = "clk13m"; }; + pwrap: pwrap@10026000 { + compatible = "mediatek,mt6873-pwrap"; + reg = <0 0x10026000 0 0x1000>; + reg-names = "pwrap"; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>; + clock-names = "spi", "wrap"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>;
Add pwrap node for mt8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)