From patchwork Tue Feb 22 10:07:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12754757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44693C433F5 for ; Tue, 22 Feb 2022 10:15:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yUu7Zmbx4zLkx2WuYe2MNBmOfDpAHgPFvA6gJOGb+qI=; b=17vF5J+GELlLwl 5ZayJENOgODIMqYpQGd04lI8ltj7BFdQGIbdKXqV5CciJIs8Msp8bfwPdJP8I4qZuxrtl/2sQX6KO 1cHkOjMjldN8HnO/HyhitAPQ633cK2DPQ4QM3AUs5lMT7qcQbxGr3UgGCn7fwbQTJGl/wszn7uIMO MqUJpgCPyRrCKoNXWBbS213001NB8ltgGVYTfMG6gHaxpzJEzz05aBTjwS0mDk8GAuIdJ4ZY4/bab INtI4BbgLoeb2MAHd/nM6PQ3+beMxyhn1jcJ2MvXBxelTMn6PYap6E2veEoYNsXD4wlFsDWmTYd/H o+GaqbiMy1vEqITcpMjA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nMSCp-008vzE-0W; Tue, 22 Feb 2022 10:15:39 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nMSAN-008ubQ-7p; Tue, 22 Feb 2022 10:13:10 +0000 X-UUID: e34b6b3055f64ae89255866d4c3e06eb-20220222 X-UUID: e34b6b3055f64ae89255866d4c3e06eb-20220222 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2102066273; Tue, 22 Feb 2022 03:12:54 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 22 Feb 2022 02:07:46 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 22 Feb 2022 18:07:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 22 Feb 2022 18:07:43 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v12 08/23] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1 Date: Tue, 22 Feb 2022 18:07:26 +0800 Message-ID: <20220222100741.30138-9-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220222100741.30138-1-nancy.lin@mediatek.com> References: <20220222100741.30138-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220222_021307_319255_29752F8B X-CRM114-Status: GOOD ( 15.71 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org MT8195 vdosys1 has more than 32 reset bits and a different reset base than other chips. Modify mmsys for support 64 bit and different reset base. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mt8195-mmsys.h | 1 + drivers/soc/mediatek/mtk-mmsys.c | 21 ++++++++++++++++----- drivers/soc/mediatek/mtk-mmsys.h | 2 ++ 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 11ba79e3275e..628098260f61 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -229,6 +229,7 @@ #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68 #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 +#define MT8195_VDO1_SW0_RST_B 0x1d0 #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40 #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50 diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 1b0024ee47a9..3f85171c980e 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -19,6 +19,8 @@ #include "mt8195-mmsys.h" #include "mt8365-mmsys.h" +#define MMSYS_SW_RESET_PER_REG 32 + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", .routes = mmsys_default_routing_table, @@ -49,12 +51,16 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", .routes = mmsys_default_routing_table, .num_routes = ARRAY_SIZE(mmsys_default_routing_table), + .sw_reset_start = MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", .routes = mmsys_mt8183_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), + .sw_reset_start = MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { @@ -75,6 +81,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), .config = mmsys_mt8195_config_table, .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table), + .sw_reset_start = MT8195_VDO1_SW0_RST_B, + .num_resets = 64, }; static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { @@ -133,18 +141,22 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l { struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); unsigned long flags; + u32 offset; u32 reg; + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); + id = id % MMSYS_SW_RESET_PER_REG; + spin_lock_irqsave(&mmsys->lock, flags); - reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B); + reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset); if (assert) reg &= ~BIT(id); else reg |= BIT(id); - writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B); + writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset); spin_unlock_irqrestore(&mmsys->lock, flags); @@ -240,10 +252,11 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return ret; } + mmsys->data = of_device_get_match_data(&pdev->dev); spin_lock_init(&mmsys->lock); mmsys->rcdev.owner = THIS_MODULE; - mmsys->rcdev.nr_resets = 32; + mmsys->rcdev.nr_resets = mmsys->data->num_resets; mmsys->rcdev.ops = &mtk_mmsys_reset_ops; mmsys->rcdev.of_node = pdev->dev.of_node; ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); @@ -252,8 +265,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return ret; } - mmsys->data = of_device_get_match_data(&pdev->dev); - #if IS_REACHABLE(CONFIG_MTK_CMDQ) ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); if (ret) diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 2694021435d2..4842102cd451 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -102,6 +102,8 @@ struct mtk_mmsys_driver_data { const unsigned int num_routes; const struct mtk_mmsys_config *config; const unsigned int num_configs; + u32 sw_reset_start; + u32 num_resets; }; /*