| Message ID | 20220318144534.17996-14-allen-kh.cheng@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add driver nodes for MT8192 SoC | expand |
Il 18/03/22 15:45, Allen-KH Cheng ha scritto: > Add mipi_tx node for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) >
On Fri, Mar 18, 2022 at 10:45:25PM +0800, Allen-KH Cheng wrote: > Add mipi_tx node for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 2648f2847993..6b769fa5b427 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1110,6 +1110,16 @@ > }; > }; > > + mipi_tx0: dsi-dphy@11e50000 { Typo here, should be dsi-phy, not dsi-dphy. Other than that, Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > + compatible = "mediatek,mt8183-mipi-tx"; > + reg = <0 0x11e50000 0 0x1000>; > + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; > + #clock-cells = <0>; > + #phy-cells = <0>; > + clock-output-names = "mipi_tx0_pll"; > + status = "disabled"; > + }; > + > i2c0: i2c@11f00000 { > compatible = "mediatek,mt8192-i2c"; > reg = <0 0x11f00000 0 0x1000>, > -- > 2.18.0 > >
On Mon, 2022-03-21 at 18:41 -0400, Nícolas F. R. A. Prado wrote: > On Fri, Mar 18, 2022 at 10:45:25PM +0800, Allen-KH Cheng wrote: > > Add mipi_tx node for mt8192 SoC. > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > --- > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index 2648f2847993..6b769fa5b427 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -1110,6 +1110,16 @@ > > }; > > }; > > > > + mipi_tx0: dsi-dphy@11e50000 { > > Typo here, should be dsi-phy, not dsi-dphy. > > Other than that, > > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Hi Nícolas Thanks for reminding me. I will pay attention next time and update in v5. Best regards, Allen > > > + compatible = "mediatek,mt8183-mipi-tx"; > > + reg = <0 0x11e50000 0 0x1000>; > > + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; > > + #clock-cells = <0>; > > + #phy-cells = <0>; > > + clock-output-names = "mipi_tx0_pll"; > > + status = "disabled"; > > + }; > > + > > i2c0: i2c@11f00000 { > > compatible = "mediatek,mt8192-i2c"; > > reg = <0 0x11f00000 0 0x1000>, > > -- > > 2.18.0 > > > >
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 2648f2847993..6b769fa5b427 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1110,6 +1110,16 @@ }; }; + mipi_tx0: dsi-dphy@11e50000 { + compatible = "mediatek,mt8183-mipi-tx"; + reg = <0 0x11e50000 0 0x1000>; + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "mipi_tx0_pll"; + status = "disabled"; + }; + i2c0: i2c@11f00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11f00000 0 0x1000>,
Add mipi_tx node for mt8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)